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79 Commits

Author SHA1 Message Date
Adrian Conlon
29edc46966 Simplify some MEMPTR usage in Intel processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-10 23:08:14 +00:00
Adrian Conlon
697bfb636d A more succinct definition of the LR35902 interrupt mechanism. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-12 22:29:37 +00:00
Adrian Conlon
a1c753d63e Couple of small tidy ups on the LR35902 implementation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:57:32 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
23f7a88480 Further 8080/Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-03 00:57:47 +00:00
Adrian Conlon
c18aeb9e63 More updates from the CPP core guidelines 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-11 11:12:09 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian Conlon
a22e59546b Tidy the gameboy core a little. Mainly by moving the execution loops into the bus class. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-24 00:04:13 +01:00
Adrian Conlon
94604b355d Tidy up include file usage. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-19 22:43:09 +01:00
Adrian Conlon
156cb66904 Split the bus into IoRegisters and "the rest" 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-05 11:24:36 +01:00
Adrian Conlon
c21d66eba4 Correct both a linux warning, and some timing anomalies. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-02 20:54:38 +01:00
Adrian Conlon
18d74b6f13 More linux changes 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-02 20:29:16 +01:00
Adrian Conlon
d2c3efac83 More linux fixes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-02 17:30:46 +01:00
Adrian Conlon
44ff68d6f3 First part of gb linux port. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-02 16:47:05 +01:00
Adrian Conlon
63f7216341 More preparation for scan line rendering. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-01 11:32:41 +01:00
Adrian Conlon
13fed631d4 Correct some cycle counting assertion failures. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-09-30 16:46:53 +01:00
Adrian Conlon
66b870bb78 First stage refactoring CPU instruction execution (to hopefully allow display interrupt interleave) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-09-30 15:28:25 +01:00
Adrian Conlon
da438ffb85 Try to get better cycle count/adjustments. 2017-09-30 00:03:42 +01:00
Adrian.Conlon
dbe5f7f8e5 Prepare the LR35902 to allow use of the Blargg gb sound library. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-23 22:56:11 +01:00
Adrian.Conlon
1a1d5ea807 Start the process of audio frame generation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-09-22 09:30:27 +01:00
Adrian.Conlon
cd63636895 Move some constants from static methods to enumerations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-09-21 20:08:37 +01:00
Adrian.Conlon
ea3f154989 Preliminary support for 16 row high sprites. Don't think it's working! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-17 09:46:28 +01:00
Adrian.Conlon
2060989ac7 Add keyboard interrupt handling (TBC) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-15 12:35:16 +01:00
Adrian.Conlon
32d1085ecb Start properly implementing IO status register read/write. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-14 23:48:49 +01:00
Adrian.Conlon
129286f1a7 Ensure LR35902 fuse tests run successfully to completion. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 01:15:28 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
ef3203d943 Tidy raster line execution a little. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 13:24:41 +01:00
Adrian.Conlon
20c126adfc Correct a couple of cycle counting issues. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-31 01:19:51 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
9da58a5af7 Merge branch 'master' of https://github.com/MoleskiCoder/EightBit 2017-08-29 17:28:24 +01:00
Adrian.Conlon
8033948aef Very small argument tidy. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-29 17:26:41 +01:00
Adrian.Conlon
ec15a2c90c Correct SP arithmetic methods: All Blargg CPU tests now pass. Hurrah! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 23:04:25 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
73a34f4fae Start a more careful documentation of the I/O registers. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-26 09:46:53 +01:00
Adrian.Conlon
246e6431ab Small correction to GB SP instructions passes a little more of the Blargg tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-25 10:33:22 +01:00
Adrian.Conlon
a087750d9c Interrupt handling doesn't use the current running cycles. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-21 09:34:17 +01:00
Adrian.Conlon
8716035396 Second stage halt implementation: allow halt state to be exited by an interrupt. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 20:09:21 +01:00
Adrian.Conlon
57e48e389f First stage "halt" reimplementation: allow the clock to run during halt, but nothing else. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 19:44:57 +01:00
Adrian.Conlon
42b0fdc23d Implement DIV timer (TBC) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 09:52:26 +01:00
Adrian.Conlon
86a4e22ae1 First stab at implementing GB timer control. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 19:00:10 +01:00
Adrian.Conlon
0457dffba4 Rewrite GB interrupt handling to properly document the trigger sequence. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 09:49:06 +01:00
Adrian.Conlon
039545bd08 Rearrange some of the shift/rotate code a little to make it easier to read. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-16 22:51:15 +01:00
Adrian.Conlon
87e97eea8c Fixes rotates and shifts zero flag use (i.e. 09 - op r,r,s now runs successfully) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-15 23:27:46 +01:00
Adrian.Conlon
6506b33436 Add comment noting GB: unique instruction. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 18:41:51 +01:00
Adrian.Conlon
fb13d9fdce Correct GB: SWAP r operation. The demoted high nibble was being effectively zeroed each time. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 21:34:19 +01:00
Adrian.Conlon
9fcb349e1f Brought the LR35902 a little closer to the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-08 13:32:51 +01:00
Adrian.Conlon
88d773708c Correct some outstanding LR35902 problems arising. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 22:04:13 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
261433bd6e Remove unneeded 16-bit operations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-27 21:44:24 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00