Adrian Conlon
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29edc46966
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Simplify some MEMPTR usage in Intel processors.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-10 23:08:14 +00:00 |
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Adrian Conlon
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1edabd79f3
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More pinout oriented method of executing instructions (especially interrupts)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-12-10 21:41:48 +00:00 |
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Adrian Conlon
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d010e3ca2f
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Start incorporating CPP core guidelines (as an experiment!)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-10 22:41:50 +00:00 |
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Adrian Conlon
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8143f8a506
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Try to correct "one definition rule" problems:
1) No forward declarations
2) No virtual methods defined inline.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-05 12:47:42 +00:00 |
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Adrian.Conlon
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64b7335a79
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Attempted move to a "BUS" oriented memory architecture (TBC!)
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
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2017-09-06 13:22:23 +01:00 |
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Adrian.Conlon
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9b43b74c28
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Rationalise some of the reset/initialise logic across pProcessor implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-01 16:01:40 +01:00 |
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Adrian.Conlon
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beca76d733
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Share instruction decoding mechanism between Intel derived processors.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-21 13:33:17 +01:00 |
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Adrian.Conlon
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3c0a1697fd
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Fetching bytes/words and stack access are more processor specific than I thought.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-07 09:27:06 +01:00 |
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Adrian.Conlon
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23108a8536
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Bring performance back to par by: inlining and static flag register access, where possible.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
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2017-06-18 18:14:39 +01:00 |
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Adrian.Conlon
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0291970427
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Further work on uniting the 8080 family processor family.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-11 21:08:40 +01:00 |
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Adrian.Conlon
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627e41bf35
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Introduce an IntelProcessor base class to allow known good implementation to be shared.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-11 09:45:34 +01:00 |
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