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61 Commits

Author SHA1 Message Date
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
97a121b8d4 Unneeded UNREACHABLEs can cause gcc to produce problematic code. TBC 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-17 23:34:27 +00:00
Adrian Conlon
dac58b121a More small tidyups in the core emulator set. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-12 01:22:28 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
c6eb68ba13 Further return by value, rather than reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-26 19:47:35 +00:00
Adrian Conlon
adf506a41e Optimisation: Prefer return by value to return by reference. ~10% speed-up! 
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-25 19:48:01 +00:00
Adrian Conlon
29edc46966 Simplify some MEMPTR usage in Intel processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-10 23:08:14 +00:00
Adrian Conlon
3bd01e211e Try to avoid so many virtual calls in the Z80 by hanging onto AF a little longer. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-09 23:30:51 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
6a47f710b9 More consistency updates between i8080 and Z80. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-04 23:41:49 +00:00
Adrian Conlon
f1b3fc1932 Correct at least some of the problems with the Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-04 21:59:38 +00:00
Adrian Conlon
23f7a88480 Further 8080/Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-03 00:57:47 +00:00
Adrian Conlon
55b989fe13 More likely/unlikely macro usages. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 14:53:35 +00:00
Adrian Conlon
9cbf76daf2 Correct a couple of LIKELY/UNLIKELY usages. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 10:34:37 +00:00
Adrian Conlon
c513f0cab1 GSL was too problematic when used with GCC. Removed. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-20 19:17:49 +00:00
Adrian Conlon
67c27d4a3e GSL + CPP core guidelines changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-18 14:29:30 +00:00
Adrian Conlon
d010e3ca2f Start incorporating CPP core guidelines (as an experiment!) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-10 22:41:50 +00:00
Adrian Conlon
b3114ed520 Correct some possible one definition rule issues. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-05 14:48:15 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian Conlon
ff2f44bbd2 ... and some more linux compatibility changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 20:15:49 +00:00
Adrian Conlon
e43801ae4b More linux compatibility updates. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 19:48:47 +00:00
Adrian Conlon
899b84baa2 Linux compatibility. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 18:47:23 +00:00
Adrian.Conlon
cae34d61d1 Ensure the Z80 unit tests run successfully to completion. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 01:04:09 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
787d9dd799 Missed an easy "assume" entry 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-08 13:38:27 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
19966f6ad8 Z80 eight bit increment/decrement can be simplified a little 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 10:05:35 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 13:33:17 +01:00
Adrian.Conlon
bbbde22322 Modify some of the Z80 daa code to better reflect bool/integer differences. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 12:17:03 +01:00
Adrian.Conlon
36fbee35fb Bring the various IntelProcessor derived processors a little closer together. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-19 13:59:28 +01:00
Adrian.Conlon
179ec7435f Whoops: adjustment of the block output flag handling was quite wrong! Thanks fuse test suite! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 20:55:32 +01:00
Adrian.Conlon
3c0a1697fd Fetching bytes/words and stack access are more processor specific than I thought. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 09:27:06 +01:00
Adrian.Conlon
f52edaf8bc Tidy up 16-bit add/subtract to properly use MEMPTR. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-03 21:42:18 +01:00
Adrian.Conlon
6af1857cb0 A few minor consistency tweaks to the i8080 and z80 processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-02 17:38:19 +01:00
Adrian.Conlon
3439523865 Some more optimisations, up to 225Mhz now. 
Reordered if statements to give "then" case "expected"
Better use of "__assume" in switch statements

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 21:25:58 +01:00
Adrian.Conlon
366c3fc601 Simplification of bitwise operators. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-29 12:19:22 +01:00
Adrian.Conlon
ea4588992d Whoops: missing switch/break was falling into an assume(0). Caused two fuse tests to fail... 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-29 10:18:07 +01:00
Adrian.Conlon
954887217f Performance mods: probably about 30% speedup: the best yet. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 00:50:34 +01:00
Adrian.Conlon
7582d65ea3 Lots more method tidy ups in search of performance. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-28 15:39:31 +01:00
Adrian.Conlon
35efc86195 Simplify the use of the REFRESH register 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-27 14:02:29 +01:00
Adrian.Conlon
c803387023 A few modifications: 
1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-26 23:22:32 +01:00
Adrian.Conlon
a7d9cb0116 Fix an optimisation instruction ordering issue: fetchByte on both rhs/lhs. 
This caused two failing tests in the debug build of the fuse test suite.

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-24 21:38:42 +01:00
Adrian.Conlon
af375ab10f Some more shared code. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 19:00:53 +01:00
Adrian.Conlon
f776379e96 Share flag adjustments across implementations using templated methods. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 16:57:38 +01:00
Adrian.Conlon
a4f8770eb0 Correct a couple of small compilation issues. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 18:08:13 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536 Bring performance back to par by: inlining and static flag register access, where possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-18 18:14:39 +01:00