Adrian Conlon
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dcba8efc83
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All experimentation on the effect of JSON parser reuser.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-12 10:10:45 +01:00 |
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Adrian Conlon
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31c3a57485
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If I've bothered to try and implement the failing test, show the actual and expected events.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 23:56:20 +01:00 |
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Adrian Conlon
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77a2c08c20
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Remove some build warnings.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 23:23:59 +01:00 |
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Adrian Conlon
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91221aa975
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Try simdjson: bloody hell, that's fast!!
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 22:09:03 +01:00 |
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Adrian Conlon
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b5074ac48c
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Create an overtly performance checking build.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 19:52:22 +01:00 |
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Adrian Conlon
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59d1e2789e
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Whoops: missed reference to RapidJson
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 19:39:37 +01:00 |
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Adrian Conlon
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7a7b0046cd
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Add an implementation that uses JsonCpp (pretty slow!)
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 19:13:05 +01:00 |
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Adrian Conlon
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f3f6452119
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Add nlohmann json parser as an option to build.
1/2 speed, compared to boost.json
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 14:59:23 +01:00 |
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Adrian Conlon
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db106b1719
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Performance: speed up message handling in TestRunner.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 11:41:50 +01:00 |
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Adrian Conlon
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5686906583
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Add nodiscard attributes, where needed
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 10:43:33 +01:00 |
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Adrian Conlon
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4be61a9d54
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Separate concerns a little between low level classes and high level classes in terms of report generation.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-11 10:20:18 +01:00 |
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Adrian Conlon
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760f5d5aec
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Correct filler memoryRead accesses to use PC() rather than the last location read.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-10 21:35:26 +01:00 |
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Adrian Conlon
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6a59bfbcd8
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First stab at using the Harte randomised processor tests. Some failures detected in the M6502 run.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-10 21:26:30 +01:00 |
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Adrian Conlon
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6c3ef821bf
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Update for latest boost v1.77
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-10-10 21:25:21 +01:00 |
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Adrian Conlon
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22506ea56c
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Extensive change warning: lots of "noexcept" and "constexpr" changes. Not sure if I'll keep all of them, but interesting...
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-07-18 14:28:40 +01:00 |
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Adrian Conlon
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2f76e901f9
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More tidying of include files for VS2019 compatibility (plus more correct!)
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-05-29 12:18:13 +01:00 |
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Adrian Conlon
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cab29e3ce4
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Tidy some code formatting. No functional changes.
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2021-04-07 21:37:30 +01:00 |
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Adrian Conlon
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2992a0e78a
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Event fire: use default arguments, where possible.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-04-07 21:36:53 +01:00 |
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Adrian Conlon
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2fa9ffd1e3
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Tidy up some C++ a little
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-04-07 21:36:09 +01:00 |
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Adrian Conlon
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b1ca06447f
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Ensure 6502 uses memory rather than bus read/write mechanism
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2021-03-08 16:44:09 +00:00 |
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Adrian Conlon
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6285a397ab
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Tidy 6502 whitespace
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2020-02-22 09:02:37 +00:00 |
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Adrian Conlon
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c8bdabf34f
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Reflect that the I/O for Intel style processors isn't part of the CPU, but attached to the Bus and access controlled by the CPU.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2020-02-09 11:51:58 +00:00 |
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Adrian Conlon
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d9466082ec
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M-Cycle accurate Z80 modifications.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-12-29 01:18:54 +00:00 |
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Adrian Conlon
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d0467421ff
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Improve compatibility with .net emulator code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-11-09 18:58:23 +00:00 |
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Adrian Conlon
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ee3ecc682d
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Add R/W pins to the MC6809 and MOS6502 processors. Hoping it'll ease peripheral development.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-09-15 12:49:32 +01:00 |
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Adrian Conlon
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254cfbe342
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Tidied up pin management to be synchronised with the .Net code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-09-06 23:55:57 +01:00 |
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Adrian Conlon
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6940a54355
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Update all EightBit projects to VS2019 (Latest SDK, C++17)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-17 11:04:29 +01:00 |
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Adrian Conlon
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5e9014997a
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Upgraded to VS2019, default SDK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-06 13:16:38 +01:00 |
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Adrian Conlon
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def1c58e9d
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Tidy project settings across the EightBit library to be more consistent.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-06 22:45:16 +01:00 |
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Adrian Conlon
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f5582df402
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Add some more M6502 documentation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:30:33 +01:00 |
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Adrian Conlon
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1a0d3ad77a
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Go through all projects for configuration consistency.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:25:44 +01:00 |
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Adrian Conlon
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f0376fa81e
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Use macros to define our device pins.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 23:17:54 +00:00 |
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Adrian Conlon
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7f853ec73f
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Add missing 6502 pin events
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 08:26:27 +00:00 |
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Adrian Conlon
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92d23d82d6
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Start big refactor of device/CPU pin usage (to allow pin events throughout).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 02:10:17 +00:00 |
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Adrian Conlon
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68030610d8
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Move to an event driven clock tick event for all CPUs
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 23:24:33 +00:00 |
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Adrian Conlon
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8b187e7614
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The clock still has to tick, even while held on RDY low, otherwise cycle timing won't work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 09:05:12 +00:00 |
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Adrian Conlon
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a90ca6ba38
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Move RDY initialisation to the CPU power-on sequence. Not strictly correct, but OK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 00:33:56 +00:00 |
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Adrian Conlon
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87d86bcd84
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Whoops: missed unneeded method declaration.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 00:08:03 +00:00 |
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Adrian Conlon
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01175cf9eb
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Add support for emulated SYNC and RDY lines. Untested, but feel close.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 23:55:27 +00:00 |
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Adrian Conlon
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047babbe7c
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Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 23:09:52 +00:00 |
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Adrian Conlon
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25321e78e7
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Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 01:32:43 +00:00 |
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Adrian Conlon
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3faec680b0
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I think this fixes one of my NES issues. The fix-up required for the PC is handled by the fetchByte associated with the BRK instruction.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:28:23 +00:00 |
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Adrian Conlon
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d7763d8215
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Profile mode no longer exists on the 6502 test program.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:08:23 +00:00 |
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Adrian Conlon
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06e2a5c947
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Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:06:07 +00:00 |
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Adrian Conlon
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b7b7c93a77
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This tidies the last of 6502 cycle accurate instruction implementations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 22:34:53 +00:00 |
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Adrian Conlon
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ad644f7013
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Tidy the 6502 instruction switch statement a little to lessen the width a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 20:51:13 +00:00 |
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Adrian Conlon
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c3d2ef51d9
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Cycle accuracy for a couple of the indexed write (store) instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 20:39:37 +00:00 |
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Adrian Conlon
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4d3be9e756
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Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 12:58:13 +00:00 |
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Adrian Conlon
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baf32cef89
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Get the memory access more correct for more of boundary crossing indexed addressing modes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 12:17:43 +00:00 |
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Adrian Conlon
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a13ad5042a
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Correct constructions of register16_t: the structure is "#ifdef"ed for different endian arrangements.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 11:27:43 +00:00 |
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