Adrian.Conlon
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64b7335a79
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Attempted move to a "BUS" oriented memory architecture (TBC!)
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
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2017-09-06 13:22:23 +01:00 |
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Adrian.Conlon
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da806bddcb
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Tidy some more Windows/Linux compatibility issues.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-03 21:30:46 +01:00 |
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Adrian.Conlon
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640b2be670
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Parts of the EightBit library become linux compatible (TBC!)
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-03 12:11:14 +01:00 |
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Adrian.Conlon
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9b43b74c28
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Rationalise some of the reset/initialise logic across pProcessor implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-01 16:01:40 +01:00 |
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Adrian.Conlon
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1eb127ed72
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Add power support to processor base class.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-31 12:13:00 +01:00 |
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Adrian.Conlon
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e70686c5de
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Some more rationalisation of processor execution/stepping strategies.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-30 23:17:34 +01:00 |
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Adrian.Conlon
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ec15a2c90c
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Correct SP arithmetic methods: All Blargg CPU tests now pass. Hurrah!
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 23:04:25 +01:00 |
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Adrian.Conlon
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d710a28526
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More consolidation of instruction implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 21:18:08 +01:00 |
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Adrian.Conlon
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329fd269ed
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Share some more code from the 6502 processor implementation.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 18:52:48 +01:00 |
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Adrian.Conlon
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59e9adf57c
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Share more of push/pop implementation across processors.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 13:19:17 +01:00 |
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Adrian.Conlon
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448ee2f09f
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Refactor the MBC implementation to allow a single point of definition.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-24 10:28:31 +01:00 |
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Adrian.Conlon
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8716035396
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Second stage halt implementation: allow halt state to be exited by an interrupt.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-20 20:09:21 +01:00 |
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Adrian.Conlon
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016b3bca59
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Switch to a memory read/write event driven model. All tests passing.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-06 17:06:48 +01:00 |
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Adrian.Conlon
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b6dd48ca63
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Some more small clarifications of shared processor implementation.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-25 18:56:43 +01:00 |
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Adrian.Conlon
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4f491f110e
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Make the 6502 a little more compatible with other processor implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-17 13:46:06 +01:00 |
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Adrian.Conlon
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8c81a27224
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"Modernise" the 6502 emulator a little. Not complete, but does successfully complete Klaus Dormann tests.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-11 21:34:01 +01:00 |
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Adrian.Conlon
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3c0a1697fd
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Fetching bytes/words and stack access are more processor specific than I thought.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-07 09:27:06 +01:00 |
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Adrian.Conlon
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c9bf24d1fa
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Tidy up register and static method access.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
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2017-06-19 13:53:00 +01:00 |
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Adrian.Conlon
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627e41bf35
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Introduce an IntelProcessor base class to allow known good implementation to be shared.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-11 09:45:34 +01:00 |
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Adrian.Conlon
|
b1aa523dcc
|
Small simplifications to base Processor class.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-10 12:42:55 +01:00 |
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Adrian.Conlon
|
d8977d32d3
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More MEMPTR clarifications.
This time to avoid temporary variables, in a similar manner to Z80 hardware.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-07 22:54:55 +01:00 |
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Adrian.Conlon
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211c75d84d
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Add Z80 processor and tests.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-05 22:39:15 +01:00 |
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Adrian.Conlon
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105032f08a
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Dump of all my C++ emulators, only Intel8080 integrated so far...
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-04 21:38:34 +01:00 |
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