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f0376fa81e
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102 Commits

Author SHA1 Message Date
Adrian Conlon
f0376fa81e Use macros to define our device pins. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 23:17:54 +00:00
Adrian Conlon
7f853ec73f Add missing 6502 pin events 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 08:26:27 +00:00
Adrian Conlon
92d23d82d6 Start big refactor of device/CPU pin usage (to allow pin events throughout). 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 02:10:17 +00:00
Adrian Conlon
68030610d8 Move to an event driven clock tick event for all CPUs 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 23:24:33 +00:00
Adrian Conlon
8b187e7614 The clock still has to tick, even while held on RDY low, otherwise cycle timing won't work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 09:05:12 +00:00
Adrian Conlon
a90ca6ba38 Move RDY initialisation to the CPU power-on sequence. Not strictly correct, but OK. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 00:33:56 +00:00
Adrian Conlon
01175cf9eb Add support for emulated SYNC and RDY lines. Untested, but feel close. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:55:27 +00:00
Adrian Conlon
047babbe7c Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:09:52 +00:00
Adrian Conlon
25321e78e7 Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 01:32:43 +00:00
Adrian Conlon
3faec680b0 I think this fixes one of my NES issues. The fix-up required for the PC is handled by the fetchByte associated with the BRK instruction. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:28:23 +00:00
Adrian Conlon
06e2a5c947 Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:06:07 +00:00
Adrian Conlon
b7b7c93a77 This tidies the last of 6502 cycle accurate instruction implementations. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 22:34:53 +00:00
Adrian Conlon
ad644f7013 Tidy the 6502 instruction switch statement a little to lessen the width a little. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 20:51:13 +00:00
Adrian Conlon
c3d2ef51d9 Cycle accuracy for a couple of the indexed write (store) instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 20:39:37 +00:00
Adrian Conlon
4d3be9e756 Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:58:13 +00:00
Adrian Conlon
baf32cef89 Get the memory access more correct for more of boundary crossing indexed addressing modes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:17:43 +00:00
Adrian Conlon
a13ad5042a Correct constructions of register16_t: the structure is "#ifdef"ed for different endian arrangements. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 11:27:43 +00:00
Adrian Conlon
3749585398 Cycle accuracy changes for BRK/RTI instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 11:13:49 +00:00
Adrian Conlon
3337f57747 More cycle accuracy changes, concentrating on stack operations. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 23:21:43 +00:00
Adrian Conlon
143e9a9e68 More cycle accuracy changes: 
1) implied instruction, pointless fetch
 2) branch pointless fetch when condition is met

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 17:23:50 +00:00
Adrian Conlon
3b7cec9c69 Spot a couple more addCycle patterns. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-04 09:17:59 +00:00
Adrian Conlon
d2e853f101 Explicitly note implied addressing mode instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-04 08:20:23 +00:00
Adrian Conlon
556e06426e Further work on the slow migration to a cycle accurate 6502 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-03 01:04:12 +00:00
Adrian Conlon
6c582f6349 Add a working(ish) 6502 ATX implementation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-30 17:12:45 +00:00
Adrian Conlon
5ade05a689 Add a bunch of undocumented 6502 instructions. Abandoned ATX implementation. Too poorly documented. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-30 12:01:23 +00:00
Adrian Conlon
815c99710a Add enough undocumented 6502 instructions to get through "nestest". 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-29 22:22:31 +00:00
Adrian Conlon
c136b306ab Use the new busRead/Write processor methods to simplify the 6502 cycle counting. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-29 22:18:01 +00:00
Adrian Conlon
adb60a6e90 Port the 6502 to the new bus architecture. 2018-12-29 19:40:02 +00:00
Adrian Conlon
7af81018c9 Modify rotate and shift instructions to be a little more understandable (6502/6809) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-11-01 19:47:21 +00:00
Adrian Conlon
4dc0becb74 Refactor the 6502 implementation to be a lot more like the MC6809. Hopefully show bugs in the latter a little more easily. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-31 23:29:13 +00:00
Adrian Conlon
fac2da9ac4 Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-27 18:41:55 +01:00
Adrian Conlon
3a4235f651 Whoops: The NMI line needs to be powered on by individual processors now it's no longer part of the Processor base class. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 22:50:18 +01:00
Adrian Conlon
535346dede Whoops: missed UNLIKELY specifier on the 6502 processor 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 13:17:14 +01:00
Adrian Conlon
c105ee37bf Have a stab at sorting out processor pin handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 12:09:26 +01:00
Adrian Conlon
6d4223c368 Start moving towards reset being just another style of interrupt. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 01:34:30 +01:00
Adrian Conlon
cc64e114a9 Start refactoring the processor classes to allow big/little endian processors to be specified. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 21:53:49 +01:00
Adrian Conlon
ed76038bfa More memptr adjustments 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 13:59:59 +01:00
Adrian Conlon
70c70af969 Sort out some exception and member initialisation rules. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-11 21:19:19 +01:00
Adrian Conlon
67487b5b6e Simplify the usage of the register16_t union. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 00:55:32 +01:00
Adrian Conlon
4b4f6b1a49 Some *small* consistency changes. Perhaps some performance gains. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-04-11 23:53:26 +01:00
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
dac58b121a More small tidyups in the core emulator set. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-12 01:22:28 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
c6eb68ba13 Further return by value, rather than reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-26 19:47:35 +00:00
Adrian Conlon
9124f10008 6502: Implement some more undocumented instructions (for the Blargg nes cpu tests) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-21 10:45:25 +00:00
Adrian Conlon
b5fee5b5d9 Make explicit the notion of page based loads in M6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 21:17:45 +00:00
Adrian Conlon
21bd8a06e6 Power on conditions are chip specific and *not* directly related to construction/destruction. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 17:50:15 +00:00
Adrian Conlon
19aea5244b The vector of instructions was good, but a switch is fastest and probably easiest to read/modify. (Running at 101Mz, 32M instructions per second) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-17 22:17:08 +00:00
Adrian Conlon
d57cb8c9be 6502: I might regret this, but move to a vector of instructions, rather than decoding them one at a time 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-16 23:54:43 +00:00
Adrian Conlon
43573ac699 6502: Rotate and shift by value, not reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-14 21:03:29 +00:00