6502/EightBit
1
0
Fork 0
mirror of https://github.com/MoleskiCoder/EightBit.git synced 2024-06-03 05:29:43 +00:00
Code Issues Projects Releases Wiki Activity
997 Commits 1 Branch 0 Tags 112 MiB
fc30360165
Commit Graph

126 Commits

Author SHA1 Message Date
Adrian Conlon
fc30360165 Minor interrupt refactoring 2024-03-21 09:20:36 +00:00
Adrian Conlon
0a6ab11fbb Simplify stack actions 2024-03-20 10:29:20 +00:00
Adrian Conlon
ad1ab61f74 Small 6502 consolidation 2024-03-18 21:38:51 +00:00
Adrian Conlon
c397b4c41b Swap fixed/unfixed page usage 2024-03-18 21:04:50 +00:00
Adrian Conlon
8b6c4a205e Lot's of small niggles corrected across the EightBit libraries 2024-03-18 13:03:41 +00:00
Adrian Conlon
f19e67875e More addressing / read tidying 2024-03-16 14:19:28 +00:00
Adrian Conlon
3ca8fc4d99 Undocumented code simplification 2024-03-15 12:34:31 +00:00
Adrian Conlon
bc71a4f3a6 read/modify/write tidy 2024-03-15 07:01:37 +00:00
Adrian Conlon
a81dec6c6e More addressing clarifications 2024-03-15 00:36:57 +00:00
Adrian Conlon
2ef9437ded intermediate step 2024-03-14 23:09:55 +00:00
Adrian Conlon
b22d7e47e5 Addressing mode simplifications 2024-03-14 14:54:52 +00:00
Adrian Conlon
a25528e11a More M6502 code consolodation etc. 2024-03-10 14:55:05 +00:00
Adrian Conlon
b582412231 RMW simplification 2024-03-07 08:31:28 +00:00
Adrian Conlon
7bfadb05b4 More address mode simplifications 2024-03-06 21:30:27 +00:00
Adrian Conlon
ee9d2bd02b More address mode clarification/simplification 2024-03-06 18:36:09 +00:00
Adrian Conlon
5cf821acb6 More address simplifications 2024-03-05 10:29:01 +00:00
Adrian Conlon
8369e0d976 Address calculations are a little easier, if they're always 16-bit 2024-03-04 17:07:22 +00:00
Adrian Conlon
92d677f9d0 Refactor M6502 address mode related code. 2024-03-04 16:58:25 +00:00
Adrian Conlon
2e29233b3b Tidy up of the M6502 page fixup code 2024-03-01 23:18:24 +00:00
Adrian Conlon
0a9a1e5d4c Complete all the undocumente M6502 features. Hurrah! 2024-01-07 16:20:58 +00:00
Adrian Conlon
72be3238f2 Undocumented M6502 instruction implemented 2024-01-07 15:52:16 +00:00
Adrian Conlon
86ef340650 Tidy arithmetic overflow handling in M6502 core 2024-01-07 14:35:12 +00:00
Adrian Conlon
4f4bc5355d Simplification of M6502 flag set/reset code 2024-01-07 14:04:41 +00:00
Adrian Conlon
7eca073a6e Make explicit swallow operations. 2024-01-07 12:15:11 +00:00
Adrian Conlon
3ebc321c59 Add an implementation of the *JAM instruction that passes HarteTest 2024-01-06 22:44:59 +00:00
Adrian Conlon
bd289ed8fb Add a working M6502 ARR implementation 2024-01-06 12:19:02 +00:00
Adrian Conlon
349bada9cc Add undocumented instructions SYA and SXA to M6502 implementation 2024-01-06 09:52:17 +00:00
Adrian Conlon
5d24a136a2 Correct loads of undocumented M6502 instructions 2024-01-05 12:52:27 +00:00
Adrian Conlon
93088b355c M6502: Unify accumulator write page boundary fixup code 2023-12-31 14:58:15 +00:00
Adrian Conlon
e4fbeebfa7 Correct problem in page boundary condition for M6502. 2023-12-31 14:32:16 +00:00
Adrian Conlon
1a5df4c8a7 More "noexcept" specifiers added to M6502 class 2022-01-24 23:00:25 +00:00
Adrian Conlon
8e0092ec9d Tidy up noexcept specification 2022-01-17 19:10:15 +00:00
Adrian Conlon
5522fde9a7 Make the flag manipulations in the 6502 implementatin a little more comprehensible 2021-12-08 19:47:35 +00:00
Adrian Conlon
03b536838b Some constexpr improvements in low level classes. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-24 11:12:23 +01:00
Adrian Conlon
22506ea56c Extensive change warning: lots of "noexcept" and "constexpr" changes. Not sure if I'll keep all of them, but interesting... 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-07-18 14:28:40 +01:00
Adrian Conlon
2fa9ffd1e3 Tidy up some C++ a little 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-04-07 21:36:09 +01:00
Adrian Conlon
b1ca06447f Ensure 6502 uses memory rather than bus read/write mechanism 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-03-08 16:44:09 +00:00
Adrian Conlon
c8bdabf34f Reflect that the I/O for Intel style processors isn't part of the CPU, but attached to the Bus and access controlled by the CPU. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2020-02-09 11:51:58 +00:00
Adrian Conlon
d0467421ff Improve compatibility with .net emulator code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-09 18:58:23 +00:00
Adrian Conlon
ee3ecc682d Add R/W pins to the MC6809 and MOS6502 processors. Hoping it'll ease peripheral development. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-15 12:49:32 +01:00
Adrian Conlon
254cfbe342 Tidied up pin management to be synchronised with the .Net code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-06 23:55:57 +01:00
Adrian Conlon
f0376fa81e Use macros to define our device pins. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 23:17:54 +00:00
Adrian Conlon
92d23d82d6 Start big refactor of device/CPU pin usage (to allow pin events throughout). 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 02:10:17 +00:00
Adrian Conlon
87d86bcd84 Whoops: missed unneeded method declaration. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 00:08:03 +00:00
Adrian Conlon
01175cf9eb Add support for emulated SYNC and RDY lines. Untested, but feel close. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:55:27 +00:00
Adrian Conlon
047babbe7c Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:09:52 +00:00
Adrian Conlon
25321e78e7 Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 01:32:43 +00:00
Adrian Conlon
06e2a5c947 Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:06:07 +00:00
Adrian Conlon
c3d2ef51d9 Cycle accuracy for a couple of the indexed write (store) instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 20:39:37 +00:00
Adrian Conlon
4d3be9e756 Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:58:13 +00:00