6502
/
EightBit
mirror of https://github.com/MoleskiCoder/EightBit.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Compare commits

base: 6502:33a0889fe1167eaebeeac4a2884ea37f5724b9af
Branches Tags
6502:master
...
compare: 6502:81aecef48b00034ec4419f0f2ccbe585c348dbfd
Branches Tags
6502:master

6 Commits
33a0889fe1 ... 81aecef48b

Author SHA1 Message Date
Adrian Conlon 81aecef48b Some performance updates for the M6502 test code. 2024-03-15 13:16:25 +00:00
Adrian Conlon 3ca8fc4d99 Undocumented code simplification 2024-03-15 12:34:31 +00:00
Adrian Conlon bc71a4f3a6 read/modify/write tidy 2024-03-15 07:01:37 +00:00
Adrian Conlon a81dec6c6e More addressing clarifications 2024-03-15 00:36:57 +00:00
Adrian Conlon 2ef9437ded intermediate step 2024-03-14 23:09:55 +00:00
Adrian Conlon b22d7e47e5 Addressing mode simplifications 2024-03-14 14:54:52 +00:00
17 changed files with 266 additions and 323 deletions
Show Stats Expand all files Collapse all files

2
Intel8080/inc/Intel8080.h
View File

@ -32,7 +32,7 @@ namespace EightBit {
Signal<Intel8080> ExecutingInstruction;
Signal<Intel8080> ExecutedInstruction;
int execute() noexcept final;
void execute() noexcept final;
int step() noexcept final;
[[nodiscard]] const register16_t& AF() const noexcept final;

6
Intel8080/src/Intel8080.cpp
View File

@ -325,10 +325,11 @@ int EightBit::Intel8080::step() noexcept {
}
}
ExecutedInstruction.fire(*this);
ASSUME(cycles() > 0);
return cycles();
}
int EightBit::Intel8080::execute() noexcept {
void EightBit::Intel8080::execute() noexcept {
const auto& decoded = getDecodedOpcode(opcode());
@ -340,9 +341,6 @@ int EightBit::Intel8080::execute() noexcept {
const auto q = decoded.q;
execute(x, y, z, p, q);
ASSUME(cycles() > 0);
return cycles();
}
void EightBit::Intel8080::execute(const int x, const int y, const int z, const int p, const int q) {

2
LR35902/inc/LR35902.h
View File

@ -47,7 +47,7 @@ namespace EightBit {
void tickMachine() { tick(4); MachineTicked.fire(); }
protected:
int execute() noexcept final;
void execute() noexcept final;
int step() noexcept final;
void handleRESET() noexcept final;

7
LR35902/src/LR35902.cpp
View File

@ -466,11 +466,12 @@ int EightBit::GameBoy::LR35902::step() noexcept {
}
}
ExecutedInstruction.fire(*this);
assert(cycles() > 0);
assert(cycles() % 4 == 0);
return cycles();
}
int EightBit::GameBoy::LR35902::execute() noexcept {
void EightBit::GameBoy::LR35902::execute() noexcept {
const auto& decoded = getDecodedOpcode(opcode());
@ -485,10 +486,6 @@ int EightBit::GameBoy::LR35902::execute() noexcept {
executeOther(x, y, z, p, q);
else
executeCB(x, y, z, p, q);
assert(cycles() > 0);
return cycles();
}
void EightBit::GameBoy::LR35902::executeCB(const int x, const int y, const int z, int, int) {

18
M6502/HarteTest_6502/checker_t.cpp
View File

@ -130,17 +130,19 @@ bool checker_t::checkState(test_t test) {
auto& cpu = runner().CPU();
auto& ram = runner().RAM();
const auto expected_cycles = test.cycles();
const auto& expected_cycles = test.cycles();
const auto& actual_cycles = m_actualCycles;
m_cycle_count_mismatch = expected_cycles.size() != actual_cycles.size();
if (m_cycle_count_mismatch)
return false;
size_t actual_idx = 0;
for (const auto expected_cycle : expected_cycles) {
if (actual_idx >= actual_cycles.size()) {
m_cycle_count_mismatch = true;
return false; // more expected cycles than actual
}
auto expected_data = expected_cycle.begin();
const auto& actual = actual_cycles.at(actual_idx++); // actual could be less than expected
const auto& actual = actual_cycles[actual_idx++];
const auto expected_address = uint16_t(int64_t(*expected_data++));
const auto actual_address = std::get<0>(actual);
@ -154,6 +156,12 @@ bool checker_t::checkState(test_t test) {
const auto actual_action = std::get<2>(actual);
check("Cycle action", expected_action.value_unsafe(), actual_action);
}
if (actual_idx < actual_cycles.size()) {
m_cycle_count_mismatch = true;
return false; // less expected cycles than actual
}
if (!m_messages.empty())
return false;

2
M6502/HarteTest_6502/checker_t.h
View File

@ -44,7 +44,7 @@ private:
void raise(std::string_view what, std::string_view expected, std::string_view actual);
template<class T>
bool check(std::string_view what, T expected, T actual) {
constexpr bool check(std::string_view what, T expected, T actual) noexcept {
const auto success = actual == expected;
if (!success)
raise(what, expected, actual);

4
M6502/HarteTest_6502/tests.cpp
View File

@ -36,7 +36,7 @@ int main() {
opcode.load();
auto test_generator = opcode.generator();
std::vector<std::string> test_names;
std::vector<std::string_view> test_names;
while (test_generator) {
const auto test = test_generator();
@ -66,7 +66,7 @@ int main() {
break;
}
test_names.push_back(std::string(std::string_view(test.name())));
test_names.push_back(test.name().get_string().value());
}
}

141
M6502/inc/mos6502.h
View File

@ -38,7 +38,7 @@ namespace EightBit {
Signal<MOS6502> ExecutingInstruction;
Signal<MOS6502> ExecutedInstruction;
int execute() noexcept final;
void execute() noexcept final;
[[nodiscard]] int step() noexcept final;
[[nodiscard]] constexpr auto& X() noexcept { return m_x; }
@ -58,19 +58,19 @@ namespace EightBit {
// Instructions with BCD effects
[[nodiscard]] virtual uint8_t sub(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
[[nodiscard]] virtual uint8_t sub(uint8_t operand, int borrow = 0) noexcept;
[[nodiscard]] void sbc() noexcept;
[[nodiscard]] uint8_t sub_b(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
[[nodiscard]] uint8_t sub_d(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
[[nodiscard]] virtual uint8_t add(uint8_t operand, uint8_t data, int carry = 0) noexcept;
[[nodiscard]] virtual uint8_t add(uint8_t operand, int carry = 0) noexcept;
[[nodiscard]] void adc() noexcept;
[[nodiscard]] uint8_t add_b(uint8_t operand, uint8_t data, int carry) noexcept;
[[nodiscard]] uint8_t add_d(uint8_t operand, uint8_t data, int carry) noexcept;
// Undocumented compound instructions (with BCD effects)
virtual void arr(uint8_t value) noexcept;
virtual void arr() noexcept;
virtual void arr_b(uint8_t value) noexcept;
virtual void arr_d(uint8_t value) noexcept;
@ -105,42 +105,29 @@ namespace EightBit {
// Addressing modes
[[nodiscard]] auto Address_Immediate() noexcept { return PC()++; }
[[nodiscard]] auto Address_Absolute() noexcept { return fetchWord(); }
[[nodiscard]] auto Address_ZeroPage() noexcept { return register16_t(fetchByte(), 0); }
[[nodiscard]] register16_t Address_ZeroPageIndirect() noexcept;
[[nodiscard]] register16_t Address_Indirect() noexcept;
[[nodiscard]] register16_t Address_ZeroPageX() noexcept;
[[nodiscard]] register16_t Address_ZeroPageY() noexcept;
[[nodiscard]] std::pair<register16_t, uint8_t> Address_AbsoluteX() noexcept;
[[nodiscard]] std::pair<register16_t, uint8_t> Address_AbsoluteY() noexcept;
[[nodiscard]] register16_t Address_IndexedIndirectX() noexcept;
[[nodiscard]] std::pair<register16_t, uint8_t> Address_IndirectIndexedY() noexcept;
[[nodiscard]] register16_t Address_relative_byte() noexcept;
void Address_Immediate() noexcept { BUS().ADDRESS() = PC()++; }
void Address_Absolute() noexcept { BUS().ADDRESS() = fetchWord(); }
void Address_ZeroPage() noexcept { BUS().ADDRESS() = register16_t(fetchByte(), 0); }
void Address_ZeroPageIndirect() noexcept;
void Address_Indirect() noexcept;
void Address_ZeroPageX() noexcept;
void Address_ZeroPageY() noexcept;
void Address_AbsoluteX() noexcept;
void Address_AbsoluteY() noexcept;
void Address_IndexedIndirectX() noexcept;
void Address_IndirectIndexedY() noexcept;
// Addressing modes, read
auto AM_Immediate() noexcept { return memoryRead(Address_Immediate()); }
auto AM_Absolute() noexcept { return memoryRead(Address_Absolute()); }
auto AM_ZeroPage() noexcept { return memoryRead(Address_ZeroPage()); }
auto AM_ZeroPageX() noexcept { return memoryRead(Address_ZeroPageX()); }
auto AM_ZeroPageY() noexcept { return memoryRead(Address_ZeroPageY()); }
auto AM_IndexedIndirectX() noexcept { return memoryRead(Address_IndexedIndirectX()); }
auto AM_AbsoluteX() noexcept {
maybe_fixup(Address_AbsoluteX());
return memoryRead();
}
auto AM_AbsoluteY() noexcept {
maybe_fixup(Address_AbsoluteY());
return memoryRead();
}
auto AM_IndirectIndexedY() noexcept {
maybe_fixup(Address_IndirectIndexedY());
return memoryRead();
}
void AM_Immediate() noexcept { Address_Immediate(); memoryRead(); }
void AM_Absolute() noexcept { Address_Absolute(); memoryRead(); }
void AM_ZeroPage() noexcept { Address_ZeroPage(); memoryRead(); }
void AM_ZeroPageX() noexcept { Address_ZeroPageX(); memoryRead(); }
void AM_ZeroPageY() noexcept { Address_ZeroPageY(); memoryRead(); }
void AM_IndexedIndirectX() noexcept { Address_IndexedIndirectX(); memoryRead(); }
void AM_AbsoluteX() noexcept { Address_AbsoluteX(); maybe_fixup(); memoryRead(); }
void AM_AbsoluteY() noexcept { Address_AbsoluteY(); maybe_fixup(); memoryRead(); }
void AM_IndirectIndexedY() noexcept { Address_IndirectIndexedY(); maybe_fixup(); memoryRead(); }
// Flag checking
@ -186,54 +173,37 @@ namespace EightBit {
return data;
}
#define FIXUP_RMW(ADDRESSING, OPERATION) \
{ \
fixup(ADDRESSING()); \
_RMW(OPERATION); \
}
#define RMW(ADDRESSING, OPERATION) \
{ \
BUS().ADDRESS() = ADDRESSING(); \
_RMW(OPERATION); \
}
#define _RMW(OPERATION) \
{ \
#define RMW(OPERATION) { \
const auto data = memoryRead(); \
const auto result = OPERATION(data); \
memoryWrite(); \
memoryWrite(result); \
}
void maybe_fixup(register16_t address, uint8_t unfixed_page) noexcept {
BUS().ADDRESS() = { address.low, unfixed_page };
if (unfixed_page != address.high) {
void maybe_fixup() noexcept {
const auto fixed_page = BUS().ADDRESS().high;
BUS().ADDRESS().high = m_unfixed_page;
if (m_unfixed_page != fixed_page) {
memoryRead();
BUS().ADDRESS().high = address.high;
BUS().ADDRESS().high = fixed_page;
}
}
void maybe_fixup(std::pair<register16_t, uint8_t> fixing) noexcept {
maybe_fixup(fixing.first, fixing.second);
}
void fixup(register16_t address, uint8_t unfixed_page) noexcept {
BUS().ADDRESS() = { address.low, unfixed_page };
void fixup() noexcept {
const auto fixed_page = BUS().ADDRESS().high;
BUS().ADDRESS().high = m_unfixed_page;
memoryRead();
BUS().ADDRESS().high = address.high;
}
void fixup(std::pair<register16_t, uint8_t> fixing) noexcept {
fixup(fixing.first, fixing.second);
BUS().ADDRESS().high = fixed_page;
}
// Status flag operations
constexpr void set_flag(int which, int condition) noexcept { P() = setBit(P(), which, condition); }
constexpr static void set_flag(uint8_t& f, int which, int condition) noexcept { f = setBit(f, which, condition); }
constexpr void set_flag(int which, int condition) noexcept { set_flag(P(), which, condition); }
constexpr void set_flag(int which) noexcept { P() = setBit(P(), which); }
constexpr void reset_flag(int which, int condition) noexcept { P() = clearBit(P(), which, condition); }
constexpr static void reset_flag(uint8_t& f, int which, int condition) noexcept { f = clearBit(f, which, condition); }
constexpr void reset_flag(int which, int condition) noexcept { reset_flag(P(), which, condition); }
constexpr void reset_flag(int which) noexcept { P() = clearBit(P(), which); }
// Chew up a cycle
@ -244,7 +214,7 @@ namespace EightBit {
// Instruction implementations
void andr() noexcept;
void bit(uint8_t operand, uint8_t data) noexcept;
void bit(uint8_t operand) noexcept;
void cmp(uint8_t first) noexcept;
[[nodiscard]] uint8_t dec(uint8_t value) noexcept;
void eorr() noexcept;
@ -282,23 +252,20 @@ namespace EightBit {
void axs() noexcept;
void jam() noexcept;
// Undocumented complicated mode implementations
void sha() noexcept { memoryWrite(A() & X() & (BUS().ADDRESS().high + 1)); }
void tas() noexcept { S() = A() & X(); sha(); }
void las() noexcept { A() = X() = S() = through(memoryRead() & S()); }
void sya() noexcept { memoryWrite(Y() & (BUS().ADDRESS().high + 1)); }
void sxa() noexcept { memoryWrite(X() & (BUS().ADDRESS().high + 1)); }
void ane() noexcept { A() = through((A() | 0xee) & X() & BUS().DATA()); }
void atx() noexcept { A() = X() = through((A() | 0xee) & BUS().DATA()); }
// SHA
void sha_AbsoluteY() noexcept;
void sha_IndirectIndexedY() noexcept;
// TAS
void tas_AbsoluteY() noexcept;
// LAS
void las_AbsoluteY() noexcept;
// SYA
void sya_AbsoluteX() noexcept;
// SXA
void sxa_AbsoluteY() noexcept;
void isb() noexcept { RMW(inc); sbc(); }
void slo() noexcept { RMW(asl); orr(); }
void rla() noexcept { RMW(rol); andr(); }
void sre() noexcept { RMW(lsr); eorr(); }
void rra() noexcept { RMW(ror); adc(); }
void dcp() noexcept { RMW(dec); cmp(A()); }
uint8_t m_x = 0; // index register X
uint8_t m_y = 0; // index register Y
@ -311,5 +278,7 @@ namespace EightBit {
bool m_handlingRESET = false;
bool m_handlingNMI = false;
bool m_handlingINT = false;
uint8_t m_unfixed_page = 0;
};
}

368
M6502/src/mos6502.cpp
View File

@ -60,6 +60,7 @@ int EightBit::MOS6502::step() noexcept {
}
ExecutedInstruction.fire(*this);
ASSUME(cycles() > 0);
return cycles();
}
@ -125,285 +126,282 @@ uint8_t EightBit::MOS6502::busRead() noexcept {
//
int EightBit::MOS6502::execute() noexcept {
void EightBit::MOS6502::execute() noexcept {
switch (opcode()) {
case 0x00: swallow_fetch(); interrupt(); break; // BRK (implied)
case 0x01: AM_IndexedIndirectX(); orr(); break; // ORA (indexed indirect X)
case 0x02: jam(); break; // *JAM
case 0x03: RMW(Address_IndexedIndirectX, asl); orr(); break; // *SLO (indexed indirect X)
case 0x03: Address_IndexedIndirectX(); slo(); break; // *SLO (indexed indirect X)
case 0x04: AM_ZeroPage(); break; // *NOP (zero page)
case 0x05: AM_ZeroPage(); orr(); break; // ORA (zero page)
case 0x06: RMW(Address_ZeroPage, asl); break; // ASL (zero page)
case 0x07: RMW(Address_ZeroPage, asl); orr(); break; // *SLO (zero page)
case 0x06: Address_ZeroPage(); RMW(asl); break; // ASL (zero page)
case 0x07: Address_ZeroPage(); slo(); break; // *SLO (zero page)
case 0x08: swallow(); php(); break; // PHP (implied)
case 0x09: AM_Immediate(); orr(); break; // ORA (immediate)
case 0x0a: swallow(); A() = asl(A()); break; // ASL A (implied)
case 0x0b: AM_Immediate(); anc(); break; // *ANC (immediate)
case 0x0c: { auto ignored = Address_Absolute(); } break; // *NOP (absolute)
case 0x0c: Address_Absolute(); break; // *NOP (absolute)
case 0x0d: AM_Absolute(); orr(); break; // ORA (absolute)
case 0x0e: RMW(Address_Absolute, asl); break; // ASL (absolute)
case 0x0f: Processor::execute(0x0e); orr(); break; // *SLO (absolute)
case 0x0e: Address_Absolute(); RMW(asl); break; // ASL (absolute)
case 0x0f: Address_Absolute(); slo(); break; // *SLO (absolute)
case 0x10: branch(negative() == 0); break; // BPL (relative)
case 0x11: AM_IndirectIndexedY(); orr(); break; // ORA (indirect indexed Y)
case 0x12: jam(); break; // *JAM
case 0x13: FIXUP_RMW(Address_IndirectIndexedY, asl); orr(); break; // *SLO (indirect indexed Y)
case 0x13: Address_IndirectIndexedY(); fixup(); slo(); break; // *SLO (indirect indexed Y)
case 0x14: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x15: AM_ZeroPageX(); orr(); break; // ORA (zero page, X)
case 0x16: RMW(Address_ZeroPageX, asl); break; // ASL (zero page, X)
case 0x17: Processor::execute(0x16); orr(); break; // *SLO (zero page, X)
case 0x16: Address_ZeroPageX(); RMW(asl); break; // ASL (zero page, X)
case 0x17: Address_ZeroPageX(); slo(); break; // *SLO (zero page, X)
case 0x18: swallow(); reset_flag(CF); break; // CLC (implied)
case 0x19: AM_AbsoluteY(); orr(); break; // ORA (absolute, Y)
case 0x1a: swallow(); break; // *NOP (implied)
case 0x1b: FIXUP_RMW(Address_AbsoluteY, asl); orr(); break; // *SLO (absolute, Y)
case 0x1c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x1b: Address_AbsoluteY(); fixup(); slo(); break; // *SLO (absolute, Y)
case 0x1c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x1d: AM_AbsoluteX(); orr(); break; // ORA (absolute, X)
case 0x1e: FIXUP_RMW(Address_AbsoluteX, asl); break; // ASL (absolute, X)
case 0x1f: Processor::execute(0x1e); orr(); break; // *SLO (absolute, X)
case 0x1e: Address_AbsoluteX(); fixup(); RMW(asl); break; // ASL (absolute, X)
case 0x1f: Address_AbsoluteX(); fixup(); slo(); break; // *SLO (absolute, X)
case 0x20: jsr(); break; // JSR (absolute)
case 0x21: AM_IndexedIndirectX(); andr(); break; // AND (indexed indirect X)
case 0x22: jam(); break; // *JAM
case 0x23: RMW(Address_IndexedIndirectX, rol); andr(); break; // *RLA (indexed indirect X)
case 0x24: bit(A(), AM_ZeroPage()); break; // BIT (zero page)
case 0x23: Address_IndexedIndirectX(); rla();; break; // *RLA (indexed indirect X)
case 0x24: AM_ZeroPage(); bit(A()); break; // BIT (zero page)
case 0x25: AM_ZeroPage(); andr(); break; // AND (zero page)
case 0x26: RMW(Address_ZeroPage, rol); break; // ROL (zero page)
case 0x27: Processor::execute(0x26); andr(); break; // *RLA (zero page)
case 0x26: Address_ZeroPage(); RMW(rol); break; // ROL (zero page)
case 0x27: Address_ZeroPage(); rla();; break; // *RLA (zero page)
case 0x28: swallow(); plp(); break; // PLP (implied)
case 0x29: AM_Immediate(); andr(); break; // AND (immediate)
case 0x2a: swallow(); A() = rol(A()); break; // ROL A (implied)
case 0x2b: AM_Immediate(); anc(); break; // *ANC (immediate)
case 0x2c: bit(A(), AM_Absolute()); break; // BIT (absolute)
case 0x2c: AM_Absolute(); bit(A()); break; // BIT (absolute)
case 0x2d: AM_Absolute(); andr(); break; // AND (absolute)
case 0x2e: RMW(Address_Absolute, rol); break; // ROL (absolute)
case 0x2f: Processor::execute(0x2e); andr(); break; // *RLA (absolute)
case 0x2e: Address_Absolute(); RMW(rol); break; // ROL (absolute)
case 0x2f: Address_Absolute(); rla();; break; // *RLA (absolute)
case 0x30: branch(negative()); break; // BMI (relative)
case 0x31: AM_IndirectIndexedY(); andr(); break; // AND (indirect indexed Y)
case 0x32: jam(); break; // *JAM
case 0x33: FIXUP_RMW(Address_IndirectIndexedY, rol); andr(); break; // *RLA (indirect indexed Y)
case 0x33: Address_IndirectIndexedY(); fixup(); rla();; break; // *RLA (indirect indexed Y)
case 0x34: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x35: AM_ZeroPageX(); andr(); break; // AND (zero page, X)
case 0x36: RMW(Address_ZeroPageX, rol); break; // ROL (zero page, X)
case 0x37: Processor::execute(0x36); andr(); break; // *RLA (zero page, X)
case 0x36: Address_ZeroPageX(); RMW(rol); break; // ROL (zero page, X)
case 0x37: Address_ZeroPageX(); rla();; break; // *RLA (zero page, X)
case 0x38: swallow(); set_flag(CF); break; // SEC (implied)
case 0x39: AM_AbsoluteY(); andr(); break; // AND (absolute, Y)
case 0x3a: swallow(); break; // *NOP (implied)
case 0x3b: FIXUP_RMW(Address_AbsoluteY, rol); andr(); break; // *RLA (absolute, Y)
case 0x3c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x3b: Address_AbsoluteY(); fixup(); rla();; break; // *RLA (absolute, Y)
case 0x3c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x3d: AM_AbsoluteX(); andr(); break; // AND (absolute, X)
case 0x3e: FIXUP_RMW(Address_AbsoluteX, rol); break; // ROL (absolute, X)
case 0x3f: Processor::execute(0x3e); andr(); break; // *RLA (absolute, X)
case 0x3e: Address_AbsoluteX(); fixup(); RMW(rol); break; // ROL (absolute, X)
case 0x3f: Address_AbsoluteX(); fixup(); rla();; break; // *RLA (absolute, X)
case 0x40: swallow(); rti(); break; // RTI (implied)
case 0x41: AM_IndexedIndirectX(); eorr(); break; // EOR (indexed indirect X)
case 0x42: jam(); break; // *JAM
case 0x43: RMW(Address_IndexedIndirectX, lsr); eorr(); break; // *SRE (indexed indirect X)
case 0x43: Address_IndexedIndirectX(); sre(); break; // *SRE (indexed indirect X)
case 0x44: AM_ZeroPage(); break; // *NOP (zero page)
case 0x45: AM_ZeroPage(); eorr(); break; // EOR (zero page)
case 0x46: RMW(Address_ZeroPage, lsr); break; // LSR (zero page)
case 0x47: Processor::execute(0x46); eorr(); break; // *SRE (zero page)
case 0x46: Address_ZeroPage(); RMW(lsr); break; // LSR (zero page)
case 0x47: Address_ZeroPage(); sre(); break; // *SRE (zero page)
case 0x48: swallow(); push(A()); break; // PHA (implied)
case 0x49: AM_Immediate(); eorr(); break; // EOR (immediate)
case 0x4a: swallow(); A() = lsr(A()); break; // LSR A (implied)
case 0x4b: AM_Immediate(); andr(); A() = lsr(A()); break; // *ASR (immediate)
case 0x4c: jump(Address_Absolute()); break; // JMP (absolute)
case 0x4c: Address_Absolute(); jump(BUS().ADDRESS()); break; // JMP (absolute)
case 0x4d: AM_Absolute(); eorr(); break; // EOR (absolute)
case 0x4e: RMW(Address_Absolute, lsr); break; // LSR (absolute)
case 0x4f: Processor::execute(0x4e); eorr(); break; // *SRE (absolute)
case 0x4e: Address_Absolute(); RMW(lsr); break; // LSR (absolute)
case 0x4f: Address_Absolute(); sre(); break; // *SRE (absolute)
case 0x50: branch(overflow() == 0); break; // BVC (relative)
case 0x51: AM_IndirectIndexedY(); eorr(); break; // EOR (indirect indexed Y)
case 0x52: jam(); break; // *JAM
case 0x53: FIXUP_RMW(Address_IndirectIndexedY, lsr); eorr(); break; // *SRE (indirect indexed Y)
case 0x53: Address_IndirectIndexedY(); fixup(); sre(); break; // *SRE (indirect indexed Y)
case 0x54: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x55: AM_ZeroPageX(); eorr(); break; // EOR (zero page, X)
case 0x56: RMW(Address_ZeroPageX, lsr); break; // LSR (zero page, X)
case 0x57: Processor::execute(0x56); eorr(); break; // *SRE (zero page, X)
case 0x56: Address_ZeroPageX(); RMW(lsr); break; // LSR (zero page, X)
case 0x57: Address_ZeroPageX(); sre(); break; // *SRE (zero page, X)
case 0x58: swallow(); reset_flag(IF); break; // CLI (implied)
case 0x59: AM_AbsoluteY(); eorr(); break; // EOR (absolute, Y)
case 0x5a: swallow(); break; // *NOP (implied)
case 0x5b: FIXUP_RMW(Address_AbsoluteY, lsr); eorr(); break; // *SRE (absolute, Y)
case 0x5c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x5b: Address_AbsoluteY(); fixup(); sre(); break; // *SRE (absolute, Y)
case 0x5c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x5d: AM_AbsoluteX(); eorr(); break; // EOR (absolute, X)
case 0x5e: FIXUP_RMW(Address_AbsoluteX, lsr); break; // LSR (absolute, X)
case 0x5f: Processor::execute(0x5e); eorr(); break; // *SRE (absolute, X)
case 0x5e: Address_AbsoluteX(); fixup(); RMW(lsr); break; // LSR (absolute, X)
case 0x5f: Address_AbsoluteX(); fixup(); sre(); break; // *SRE (absolute, X)
case 0x60: swallow(); rts(); break; // RTS (implied)
case 0x61: AM_IndexedIndirectX(); adc(); break; // ADC (indexed indirect X)
case 0x62: jam(); break; // *JAM
case 0x63: RMW(Address_IndexedIndirectX, ror); adc(); break; // *RRA (indexed indirect X)
case 0x63: Address_IndexedIndirectX(); rra(); break; // *RRA (indexed indirect X)
case 0x64: AM_ZeroPage(); break; // *NOP (zero page)
case 0x65: AM_ZeroPage(); adc(); break; // ADC (zero page)
case 0x66: RMW(Address_ZeroPage, ror); break; // ROR (zero page)
case 0x67: Processor::execute(0x66); adc(); break; // *RRA (zero page)
case 0x66: Address_ZeroPage(); RMW(ror); break; // ROR (zero page)
case 0x67: Address_ZeroPage(); rra(); break; // *RRA (zero page)
case 0x68: swallow(); swallow_stack(); A() = through(pop()); break; // PLA (implied)
case 0x69: AM_Immediate(); adc(); break; // ADC (immediate)
case 0x6a: swallow(); A() = ror(A()); break; // ROR A (implied)
case 0x6b: arr(AM_Immediate()); break; // *ARR (immediate)
case 0x6c: jump(Address_Indirect()); break; // JMP (indirect)
case 0x6b: AM_Immediate(); arr(); break; // *ARR (immediate)
case 0x6c: Address_Indirect(); jump(BUS().ADDRESS()); break; // JMP (indirect)
case 0x6d: AM_Absolute(); adc(); break; // ADC (absolute)
case 0x6e: RMW(Address_Absolute, ror); break; // ROR (absolute)
case 0x6f: Processor::execute(0x6e); adc(); break; // *RRA (absolute)
case 0x6e: Address_Absolute(); RMW(ror); break; // ROR (absolute)
case 0x6f: Address_Absolute(); rra(); break; // *RRA (absolute)
case 0x70: branch(overflow()); break; // BVS (relative)
case 0x71: AM_IndirectIndexedY(); adc(); break; // ADC (indirect indexed Y)
case 0x72: jam(); break; // *JAM
case 0x73: FIXUP_RMW(Address_IndirectIndexedY, ror); adc(); break; // *RRA (indirect indexed Y)
case 0x73: Address_IndirectIndexedY(); fixup(); rra(); break; // *RRA (indirect indexed Y)
case 0x74: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x75: AM_ZeroPageX(); adc(); break; // ADC (zero page, X)
case 0x76: RMW(Address_ZeroPageX, ror); break; // ROR (zero page, X)
case 0x77: Processor::execute(0x76); adc(); break; // *RRA (zero page, X)
case 0x76: Address_ZeroPageX(); RMW(ror); break; // ROR (zero page, X)
case 0x77: Address_ZeroPageX(); rra(); break; // *RRA (zero page, X)
case 0x78: swallow(); set_flag(IF); break; // SEI (implied)
case 0x79: AM_AbsoluteY(); adc(); break; // ADC (absolute, Y)
case 0x7a: swallow(); break; // *NOP (implied)
case 0x7b: FIXUP_RMW(Address_AbsoluteY, ror); adc(); break; // *RRA (absolute, Y)
case 0x7c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x7b: Address_AbsoluteY(); fixup(); rra(); break; // *RRA (absolute, Y)
case 0x7c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x7d: AM_AbsoluteX(); adc(); break; // ADC (absolute, X)
case 0x7e: FIXUP_RMW(Address_AbsoluteX, ror); break; // ROR (absolute, X)
case 0x7f: Processor::execute(0x7e); adc(); break; // *RRA (absolute, X)
case 0x7e: Address_AbsoluteX(); fixup(); RMW(ror); break; // ROR (absolute, X)
case 0x7f: Address_AbsoluteX(); fixup(); rra(); break; // *RRA (absolute, X)
case 0x80: AM_Immediate(); break; // *NOP (immediate)
case 0x81: memoryWrite(Address_IndexedIndirectX(), A()); break; // STA (indexed indirect X)
case 0x81: Address_IndexedIndirectX(); memoryWrite(A()); break; // STA (indexed indirect X)
case 0x82: AM_Immediate(); break; // *NOP (immediate)
case 0x83: memoryWrite(Address_IndexedIndirectX(), A() & X()); break; // *SAX (indexed indirect X)
case 0x84: memoryWrite(Address_ZeroPage(), Y()); break; // STY (zero page)
case 0x85: memoryWrite(Address_ZeroPage(), A()); break; // STA (zero page)
case 0x86: memoryWrite(Address_ZeroPage(), X()); break; // STX (zero page)
case 0x87: memoryWrite(Address_ZeroPage(), A() & X()); break; // *SAX (zero page)
case 0x83: Address_IndexedIndirectX(); memoryWrite(A() & X()); break; // *SAX (indexed indirect X)
case 0x84: Address_ZeroPage(); memoryWrite(Y()); break; // STY (zero page)
case 0x85: Address_ZeroPage(); memoryWrite(A()); break; // STA (zero page)
case 0x86: Address_ZeroPage(); memoryWrite(X()); break; // STX (zero page)
case 0x87: Address_ZeroPage(); memoryWrite(A() & X()); break; // *SAX (zero page)
case 0x88: swallow(); Y() = dec(Y()); break; // DEY (implied)
case 0x89: AM_Immediate(); break; // *NOP (immediate)
case 0x8a: swallow(); A() = through(X()); break; // TXA (implied)
case 0x8b: A() = through((A() | 0xee) & X() & AM_Immediate()); break; // *ANE (immediate)
case 0x8c: memoryWrite(Address_Absolute(), Y()); break; // STY (absolute)
case 0x8d: memoryWrite(Address_Absolute(), A()); break; // STA (absolute)
case 0x8e: memoryWrite(Address_Absolute(), X()); break; // STX (absolute)
case 0x8f: memoryWrite(Address_Absolute(), A() & X()); break; // *SAX (absolute)
case 0x8b: AM_Immediate(); ane(); break; // *ANE (immediate)
case 0x8c: Address_Absolute(); memoryWrite(Y()); break; // STY (absolute)
case 0x8d: Address_Absolute(); memoryWrite(A()); break; // STA (absolute)
case 0x8e: Address_Absolute(); memoryWrite(X()); break; // STX (absolute)
case 0x8f: Address_Absolute(); memoryWrite(A() & X()); break; // *SAX (absolute)
case 0x90: branch(carry() == 0); break; // BCC (relative)
case 0x91: fixup(Address_IndirectIndexedY()); memoryWrite(A()); break; // STA (indirect indexed Y)
case 0x91: Address_IndirectIndexedY(); fixup(); memoryWrite(A()); break; // STA (indirect indexed Y)
case 0x92: jam(); break; // *JAM
case 0x93: sha_IndirectIndexedY(); break; // *SHA (indirect indexed, Y)
case 0x94: memoryWrite(Address_ZeroPageX(), Y()); break; // STY (zero page, X)
case 0x95: memoryWrite(Address_ZeroPageX(), A()); break; // STA (zero page, X)
case 0x96: memoryWrite(Address_ZeroPageY(), X()); break; // STX (zero page, Y)
case 0x97: memoryWrite(Address_ZeroPageY(), A() & X()); break; // *SAX (zero page, Y)
case 0x93: Address_IndirectIndexedY(); fixup(); sha(); break; // *SHA (indirect indexed, Y)
case 0x94: Address_ZeroPageX(); memoryWrite(Y()); break; // STY (zero page, X)
case 0x95: Address_ZeroPageX(); memoryWrite(A()); break; // STA (zero page, X)
case 0x96: Address_ZeroPageY(); memoryWrite(X()); break; // STX (zero page, Y)
case 0x97: Address_ZeroPageY(); memoryWrite(A() & X()); break; // *SAX (zero page, Y)
case 0x98: swallow(); A() = through(Y()); break; // TYA (implied)
case 0x99: fixup(Address_AbsoluteY()); memoryWrite(A()); break; // STA (absolute, Y)
case 0x99: Address_AbsoluteY(); fixup(); memoryWrite(A()); break; // STA (absolute, Y)
case 0x9a: swallow(); S() = X(); break; // TXS (implied)
case 0x9b: tas_AbsoluteY(); break; // *TAS (absolute, Y)
case 0x9c: sya_AbsoluteX(); break; // *SYA (absolute, X)
case 0x9d: fixup(Address_AbsoluteX()); memoryWrite(A()); break; // STA (absolute, X)
case 0x9e: sxa_AbsoluteY(); break; // *SXA (absolute, Y)
case 0x9f: sha_AbsoluteY(); break; // *SHA (absolute, Y)
case 0x9b: Address_AbsoluteY(); fixup(); tas(); break; // *TAS (absolute, Y)
case 0x9c: Address_AbsoluteX(); fixup(); sya(); break; // *SYA (absolute, X)
case 0x9d: Address_AbsoluteX(); fixup(); memoryWrite(A()); break; // STA (absolute, X)
case 0x9e: Address_AbsoluteY(); fixup(); sxa(); break; // *SXA (absolute, Y)
case 0x9f: Address_AbsoluteY(); fixup(); sha(); break; // *SHA (absolute, Y)
case 0xa0: Y() = through(AM_Immediate()); break; // LDY (immediate)
case 0xa1: A() = through(AM_IndexedIndirectX()); break; // LDA (indexed indirect X)
case 0xa2: X() = through(AM_Immediate()); break; // LDX (immediate)
case 0xa3: A() = X() = through(AM_IndexedIndirectX()); break; // *LAX (indexed indirect X)
case 0xa4: Y() = through(AM_ZeroPage()); break; // LDY (zero page)
case 0xa5: A() = through(AM_ZeroPage()); break; // LDA (zero page)
case 0xa6: X() = through(AM_ZeroPage()); break; // LDX (zero page)
case 0xa7: A() = X() = through(AM_ZeroPage()); break; // *LAX (zero page)
case 0xa0: AM_Immediate(); Y() = through(BUS().DATA()); break; // LDY (immediate)
case 0xa1: AM_IndexedIndirectX(); A() = through(BUS().DATA()); break; // LDA (indexed indirect X)
case 0xa2: AM_Immediate(); X() = through(BUS().DATA()); break; // LDX (immediate)
case 0xa3: AM_IndexedIndirectX(); A() = X() = through(BUS().DATA()); break; // *LAX (indexed indirect X)
case 0xa4: AM_ZeroPage(); Y() = through(BUS().DATA()); break; // LDY (zero page)
case 0xa5: AM_ZeroPage(); A() = through(BUS().DATA()); break; // LDA (zero page)
case 0xa6: AM_ZeroPage(); X() = through(BUS().DATA()); break; // LDX (zero page)
case 0xa7: AM_ZeroPage(); A() = X() = through(BUS().DATA()); break; // *LAX (zero page)
case 0xa8: swallow(); Y() = through(A()); break; // TAY (implied)
case 0xa9: A() = through(AM_Immediate()); break; // LDA (immediate)
case 0xa9: AM_Immediate(); A() = through(BUS().DATA()); break; // LDA (immediate)
case 0xaa: swallow(); X() = through(A()); break; // TAX (implied)
case 0xab: A() = X() = through((A() | 0xee) & AM_Immediate()); break; // *ATX (immediate)
case 0xac: Y() = through(AM_Absolute()); break; // LDY (absolute)
case 0xad: A() = through(AM_Absolute()); break; // LDA (absolute)
case 0xae: X() = through(AM_Absolute()); break; // LDX (absolute)
case 0xaf: A() = X() = through(AM_Absolute()); break; // *LAX (absolute)
case 0xab: AM_Immediate(); atx(); break; // *ATX (immediate)
case 0xac: AM_Absolute(); Y() = through(BUS().DATA()); break; // LDY (absolute)
case 0xad: AM_Absolute(); A() = through(BUS().DATA()); break; // LDA (absolute)
case 0xae: AM_Absolute(); X() = through(BUS().DATA()); break; // LDX (absolute)
case 0xaf: AM_Absolute(); A() = X() = through(BUS().DATA()); break; // *LAX (absolute)
case 0xb0: branch(carry()); break; // BCS (relative)
case 0xb1: A() = through(AM_IndirectIndexedY()); break; // LDA (indirect indexed Y)
case 0xb1: AM_IndirectIndexedY(); A() = through(BUS().DATA()); break; // LDA (indirect indexed Y)
case 0xb2: jam(); break; // *JAM
case 0xb3: A() = X() = through(AM_IndirectIndexedY()); break; // *LAX (indirect indexed Y)
case 0xb4: Y() = through(AM_ZeroPageX()); break; // LDY (zero page, X)
case 0xb5: A() = through(AM_ZeroPageX()); break; // LDA (zero page, X)
case 0xb6: X() = through(AM_ZeroPageY()); break; // LDX (zero page, Y)
case 0xb7: A() = X() = through(AM_ZeroPageY()); break; // *LAX (zero page, Y)
case 0xb3: AM_IndirectIndexedY(); A() = X() = through(BUS().DATA()); break; // *LAX (indirect indexed Y)
case 0xb4: AM_ZeroPageX(); Y() = through(BUS().DATA()); break; // LDY (zero page, X)
case 0xb5: AM_ZeroPageX(); A() = through(BUS().DATA()); break; // LDA (zero page, X)
case 0xb6: AM_ZeroPageY(); X() = through(BUS().DATA()); break; // LDX (zero page, Y)
case 0xb7: AM_ZeroPageY(); A() = X() = through(BUS().DATA()); break; // *LAX (zero page, Y)
case 0xb8: swallow(); reset_flag(VF); break; // CLV (implied)
case 0xb9: A() = through(AM_AbsoluteY()); break; // LDA (absolute, Y)
case 0xb9: AM_AbsoluteY(); A() = through(BUS().DATA()); break; // LDA (absolute, Y)
case 0xba: swallow(); X() = through(S()); break; // TSX (implied)
case 0xbb: las_AbsoluteY(); break; // *LAS (absolute, Y)
case 0xbc: Y() = through(AM_AbsoluteX()); break; // LDY (absolute, X)
case 0xbd: A() = through(AM_AbsoluteX()); break; // LDA (absolute, X)
case 0xbe: X() = through(AM_AbsoluteY()); break; // LDX (absolute, Y)
case 0xbf: A() = X() = through(AM_AbsoluteY()); break; // *LAX (absolute, Y)
case 0xbb: Address_AbsoluteY(); maybe_fixup(); las(); break; // *LAS (absolute, Y)
case 0xbc: AM_AbsoluteX(); Y() = through(BUS().DATA()); break; // LDY (absolute, X)
case 0xbd: AM_AbsoluteX(); A() = through(BUS().DATA()); break; // LDA (absolute, X)
case 0xbe: AM_AbsoluteY(); X() = through(BUS().DATA()); break; // LDX (absolute, Y)
case 0xbf: AM_AbsoluteY(); A() = X() = through(BUS().DATA()); break; // *LAX (absolute, Y)
case 0xc0: AM_Immediate(); cmp(Y()); break; // CPY (immediate)
case 0xc1: AM_IndexedIndirectX(); cmp(A()); break; // CMP (indexed indirect X)
case 0xc2: AM_Immediate(); break; // *NOP (immediate)
case 0xc3: RMW(Address_IndexedIndirectX, dec); cmp(A()); break; // *DCP (indexed indirect X)
case 0xc3: Address_IndexedIndirectX(); dcp(); break; // *DCP (indexed indirect X)
case 0xc4: AM_ZeroPage(); cmp(Y()); break; // CPY (zero page)
case 0xc5: AM_ZeroPage(); cmp(A()); break; // CMP (zero page)
case 0xc6: RMW(Address_ZeroPage, dec); break; // DEC (zero page)
case 0xc7: Processor::execute(0xc6); cmp(A()); break; // *DCP (zero page)
case 0xc6: Address_ZeroPage(); RMW(dec); break; // DEC (zero page)
case 0xc7: Address_ZeroPage(); dcp(); break; // *DCP (zero page)
case 0xc8: swallow(); Y() = inc(Y()); break; // INY (implied)
case 0xc9: AM_Immediate(); cmp(A()); break; // CMP (immediate)
case 0xca: swallow(); X() = dec(X()); break; // DEX (implied)
case 0xcb: AM_Immediate(); axs(); break; // *AXS (immediate)
case 0xcc: AM_Absolute(); cmp(Y()); break; // CPY (absolute)
case 0xcd: AM_Absolute(); cmp(A()); break; // CMP (absolute)
case 0xce: RMW(Address_Absolute, dec); break; // DEC (absolute)
case 0xcf: Processor::execute(0xce); cmp(A()); break; // *DCP (absolute)
case 0xce: Address_Absolute(); RMW(dec); break; // DEC (absolute)
case 0xcf: Address_Absolute(); dcp(); break; // *DCP (absolute)
case 0xd0: branch(zero() == 0); break; // BNE (relative)
case 0xd1: AM_IndirectIndexedY(); cmp(A()); break; // CMP (indirect indexed Y)
case 0xd2: jam(); break; // *JAM
case 0xd3: FIXUP_RMW(Address_IndirectIndexedY, dec); cmp(A()); break; // *DCP (indirect indexed Y)
case 0xd3: Address_IndirectIndexedY(); fixup(); dcp(); break; // *DCP (indirect indexed Y)
case 0xd4: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xd5: AM_ZeroPageX(); cmp(A()); break; // CMP (zero page, X)
case 0xd6: RMW(Address_ZeroPageX, dec); break; // DEC (zero page, X)
case 0xd7: Processor::execute(0xd6); cmp(A()); break; // *DCP (zero page, X)
case 0xd6: Address_ZeroPageX(); RMW(dec); break; // DEC (zero page, X)
case 0xd7: Address_ZeroPageX(); dcp(); break; // *DCP (zero page, X)
case 0xd8: swallow(); reset_flag(DF); break; // CLD (implied)
case 0xd9: AM_AbsoluteY(); cmp(A()); break; // CMP (absolute, Y)
case 0xda: swallow(); break; // *NOP (implied)
case 0xdb: FIXUP_RMW(Address_AbsoluteY, dec); cmp(A()); break; // *DCP (absolute, Y)
case 0xdc: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0xdb: Address_AbsoluteY(); fixup(); dcp(); break; // *DCP (absolute, Y)
case 0xdc: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0xdd: AM_AbsoluteX(); cmp(A()); break; // CMP (absolute, X)
case 0xde: FIXUP_RMW(Address_AbsoluteX, dec); break; // DEC (absolute, X)
case 0xdf: Processor::execute(0xde); cmp(A()); break; // *DCP (absolute, X)
case 0xde: Address_AbsoluteX(); fixup(); RMW(dec); break; // DEC (absolute, X)
case 0xdf: Address_AbsoluteX(); fixup(); dcp(); break; // *DCP (absolute, X)
case 0xe0: AM_Immediate(); cmp(X()); break; // CPX (immediate)
case 0xe1: AM_IndexedIndirectX(); sbc(); break; // SBC (indexed indirect X)
case 0xe2: AM_Immediate(); break; // *NOP (immediate)
case 0xe3: RMW(Address_IndexedIndirectX, inc); sbc(); break; // *ISB (indexed indirect X)
case 0xe3: Address_IndexedIndirectX(); isb(); break; // *ISB (indexed indirect X)
case 0xe4: AM_ZeroPage(); cmp(X()); break; // CPX (zero page)
case 0xe5: AM_ZeroPage(); sbc(); break; // SBC (zero page)
case 0xe6: RMW(Address_ZeroPage, inc); break; // INC (zero page)
case 0xe7: Processor::execute(0xe6); sbc(); break; // *ISB (zero page)
case 0xe6: Address_ZeroPage(); RMW(inc); break; // INC (zero page)
case 0xe7: Address_ZeroPage(); isb(); break; // *ISB (zero page)
case 0xe8: swallow(); X() = inc(X()); break; // INX (implied)
case 0xe9: AM_Immediate(); sbc(); break; // SBC (immediate)
case 0xea: swallow(); break; // NOP (implied)
case 0xeb: AM_Immediate(); sbc(); break; // *SBC (immediate)
case 0xec: AM_Absolute(); cmp(X()); break; // CPX (absolute)
case 0xed: AM_Absolute(); sbc(); break; // SBC (absolute)
case 0xee: RMW(Address_Absolute, inc); break; // INC (absolute)
case 0xef: Processor::execute(0xee); sbc(); break; // *ISB (absolute)
case 0xee: Address_Absolute(); RMW(inc); break; // INC (absolute)
case 0xef: Address_Absolute(); isb(); break; // *ISB (absolute)
case 0xf0: branch(zero()); break; // BEQ (relative)
case 0xf1: AM_IndirectIndexedY(); sbc(); break; // SBC (indirect indexed Y)
case 0xf2: jam(); break; // *JAM
case 0xf3: FIXUP_RMW(Address_IndirectIndexedY, inc); sbc(); break; // *ISB (indirect indexed Y)
case 0xf3: Address_IndirectIndexedY(); fixup(); isb(); break; // *ISB (indirect indexed Y)
case 0xf4: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xf5: AM_ZeroPageX(); sbc(); break; // SBC (zero page, X)
case 0xf6: RMW(Address_ZeroPageX, inc); break; // INC (zero page, X)
case 0xf7: Processor::execute(0xf6); sbc(); break; // *ISB (zero page, X)
case 0xf6: Address_ZeroPageX(); RMW(inc); break; // INC (zero page, X)
case 0xf7: Address_ZeroPageX(); isb(); break; // *ISB (zero page, X)
case 0xf8: swallow(); set_flag(DF); break; // SED (implied)
case 0xf9: AM_AbsoluteY(); sbc(); break; // SBC (absolute, Y)
case 0xfa: swallow(); break; // *NOP (implied)
case 0xfb: FIXUP_RMW(Address_AbsoluteY, inc); sbc(); break; // *ISB (absolute, Y)
case 0xfc: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0xfb: Address_AbsoluteY(); fixup(); isb(); break; // *ISB (absolute, Y)
case 0xfc: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0xfd: AM_AbsoluteX(); sbc(); break; // SBC (absolute, X)
case 0xfe: FIXUP_RMW(Address_AbsoluteX, inc); break; // INC (absolute, X)
case 0xff: Processor::execute(0xfe); sbc(); break; // *ISB (absolute, X)
case 0xfe: Address_AbsoluteX(); fixup(); RMW(inc); break; // INC (absolute, X)
case 0xff: Address_AbsoluteX(); fixup(); isb(); break; // *ISB (absolute, X)
}
ASSUME(cycles() > 0);
return cycles();
}
////
@ -425,56 +423,59 @@ void EightBit::MOS6502::dummyPush(uint8_t value) noexcept {
////
EightBit::register16_t EightBit::MOS6502::Address_ZeroPageIndirect() noexcept {
return Processor::getWordPaged(Address_ZeroPage());
void EightBit::MOS6502::Address_ZeroPageIndirect() noexcept {
Address_ZeroPage();
BUS().ADDRESS() = getWordPaged();
}
EightBit::register16_t EightBit::MOS6502::Address_Indirect() noexcept {
return Processor::getWordPaged(Address_Absolute());
void EightBit::MOS6502::Address_Indirect() noexcept {
Address_Absolute();
BUS().ADDRESS() = getWordPaged();
}
EightBit::register16_t EightBit::MOS6502::Address_ZeroPageX() noexcept {
void EightBit::MOS6502::Address_ZeroPageX() noexcept {
AM_ZeroPage();
return register16_t(BUS().ADDRESS().low + X(), 0);
BUS().ADDRESS().low += X();
}
EightBit::register16_t EightBit::MOS6502::Address_ZeroPageY() noexcept {
void EightBit::MOS6502::Address_ZeroPageY() noexcept {
AM_ZeroPage();
return register16_t(BUS().ADDRESS().low + Y(), 0);
BUS().ADDRESS().low += Y();
}
std::pair<EightBit::register16_t, uint8_t> EightBit::MOS6502::Address_AbsoluteX() noexcept {
const auto address = Address_Absolute();
return { address + X(), address.high };
void EightBit::MOS6502::Address_AbsoluteX() noexcept {
Address_Absolute();
m_unfixed_page = BUS().ADDRESS().high;
BUS().ADDRESS() += X();
}
std::pair<EightBit::register16_t, uint8_t> EightBit::MOS6502::Address_AbsoluteY() noexcept {
const auto address = Address_Absolute();
return { address + Y(), address.high };
void EightBit::MOS6502::Address_AbsoluteY() noexcept {
Address_Absolute();
m_unfixed_page = BUS().ADDRESS().high;
BUS().ADDRESS() += Y();
}
EightBit::register16_t EightBit::MOS6502::Address_IndexedIndirectX() noexcept {
return Processor::getWordPaged(Address_ZeroPageX());
void EightBit::MOS6502::Address_IndexedIndirectX() noexcept {
Address_ZeroPageX();
BUS().ADDRESS() = getWordPaged();
}
std::pair<EightBit::register16_t, uint8_t> EightBit::MOS6502::Address_IndirectIndexedY() noexcept {
const auto address = Address_ZeroPageIndirect();
return { address + Y(), address.high };
}
EightBit::register16_t EightBit::MOS6502::Address_relative_byte() noexcept {
return PC() + int8_t(fetchByte());
void EightBit::MOS6502::Address_IndirectIndexedY() noexcept {
Address_ZeroPageIndirect();
m_unfixed_page = BUS().ADDRESS().high;
BUS().ADDRESS() += Y();
}
////
void EightBit::MOS6502::branch(const int condition) noexcept {
const auto destination = Address_relative_byte();
const auto relative = int8_t(fetchByte());
if (condition) {
swallow();
const auto page = PC().high;
jump(destination);
maybe_fixup(PC(), page);
m_unfixed_page = PC().high;
jump(PC() + relative);
BUS().ADDRESS() = PC();
maybe_fixup();
}
}
@ -483,16 +484,16 @@ void EightBit::MOS6502::branch(const int condition) noexcept {
void EightBit::MOS6502::sbc() noexcept {
const auto operand = A();
const auto data = BUS().DATA();
A() = sub(operand, data, carry(~P()));
A() = sub(operand, carry(~P()));
const auto difference = m_intermediate;
adjustOverflow_subtract(operand, BUS().DATA(), difference.low);
adjustNZ(difference.low);
adjustOverflow_subtract(operand, data, difference.low);
reset_flag(CF, difference.high);
}
uint8_t EightBit::MOS6502::sub(const uint8_t operand, const uint8_t data, const int borrow) noexcept {
uint8_t EightBit::MOS6502::sub(const uint8_t operand, const int borrow) noexcept {
const auto data = BUS().DATA();
return decimal() ? sub_d(operand, data, borrow) : sub_b(operand, data, borrow);
}
@ -518,10 +519,11 @@ uint8_t EightBit::MOS6502::sub_d(const uint8_t operand, const uint8_t data, cons
}
void EightBit::MOS6502::adc() noexcept {
A() = add(A(), BUS().DATA(), carry());
A() = add(A(), carry());
}
uint8_t EightBit::MOS6502::add(uint8_t operand, uint8_t data, int carrying) noexcept {
uint8_t EightBit::MOS6502::add(uint8_t operand, int carrying) noexcept {
const auto data = BUS().DATA();
return decimal() ? add_d(operand, data, carrying) : add_b(operand, data, carrying);
}
@ -563,7 +565,8 @@ void EightBit::MOS6502::andr() noexcept {
A() = through(A() & BUS().DATA());
}
void EightBit::MOS6502::bit(const uint8_t operand, const uint8_t data) noexcept {
void EightBit::MOS6502::bit(const uint8_t operand) noexcept {
const auto data = BUS().DATA();
set_flag(VF, overflow(data));
adjustZero(operand & data);
adjustNegative(data);
@ -627,7 +630,8 @@ void EightBit::MOS6502::anc() noexcept {
set_flag(CF, A() & Bit7);
}
void EightBit::MOS6502::arr(const uint8_t value) noexcept {
void EightBit::MOS6502::arr() noexcept {
const auto value = BUS().DATA();
decimal() ? arr_d(value) : arr_b(value);
}
@ -667,35 +671,3 @@ void EightBit::MOS6502::jam() noexcept {
memoryRead();
memoryRead();
}
//
void EightBit::MOS6502::sha_AbsoluteY() noexcept {
fixup(Address_AbsoluteY());
memoryWrite(A() & X() & (BUS().ADDRESS().high + 1));
}
void EightBit::MOS6502::sha_IndirectIndexedY() noexcept {
fixup(Address_IndirectIndexedY());
memoryWrite(A() & X() & (BUS().ADDRESS().high + 1));
}
void EightBit::MOS6502::sya_AbsoluteX() noexcept {
fixup(Address_AbsoluteX());
memoryWrite(Y() & (BUS().ADDRESS().high + 1));
}
void EightBit::MOS6502::tas_AbsoluteY() noexcept {
S() = A() & X();
sha_AbsoluteY();
}
void EightBit::MOS6502::las_AbsoluteY() noexcept {
maybe_fixup(Address_AbsoluteY());
A() = X() = S() = through(memoryRead() & S());
}
void EightBit::MOS6502::sxa_AbsoluteY() noexcept {
fixup(Address_AbsoluteY());
memoryWrite(X() & (BUS().ADDRESS().high + 1));
}

2
MC6809/inc/mc6809.h
View File

@ -66,7 +66,7 @@ namespace EightBit {
Signal<mc6809> ExecutingInstruction;
Signal<mc6809> ExecutedInstruction;
int execute() noexcept final;
void execute() noexcept final;
[[nodiscard]] int step() noexcept final;
[[nodiscard]] constexpr auto& D() noexcept { return m_d; }

5
MC6809/src/mc6809.cpp
View File

@ -39,6 +39,7 @@ int EightBit::mc6809::step() noexcept {
Processor::execute(fetchByte());
}
ExecutedInstruction.fire(*this);
assert(cycles() > 0);
return cycles();
}
@ -139,7 +140,7 @@ void EightBit::mc6809::ret() noexcept {
//
int EightBit::mc6809::execute() noexcept {
void EightBit::mc6809::execute() noexcept {
lowerBA();
lowerBS();
const bool prefixed = m_prefix10 || m_prefix11;
@ -152,8 +153,6 @@ int EightBit::mc6809::execute() noexcept {
else
execute11();
}
assert(cycles() > 0);
return cycles();
}
void EightBit::mc6809::executeUnprefixed() {

4
Ricoh2A03/inc/Ricoh2A03.h
View File

@ -11,7 +11,7 @@ namespace EightBit {
virtual ~Ricoh2A03() = default;
protected:
virtual uint8_t sub(uint8_t operand, uint8_t data, int borrow) noexcept final;
virtual uint8_t add(uint8_t operand, uint8_t data, int carry) noexcept final;
virtual uint8_t sub(uint8_t operand, int borrow) noexcept final;
virtual uint8_t add(uint8_t operand, int carry) noexcept final;
};
}

6
Ricoh2A03/src/Ricoh2A03.cpp
View File

@ -5,10 +5,12 @@ EightBit::Ricoh2A03::Ricoh2A03(Bus& bus)
: MOS6502(bus) {
}
uint8_t EightBit::Ricoh2A03::sub(uint8_t operand, uint8_t data, int borrow) noexcept {
uint8_t EightBit::Ricoh2A03::sub(uint8_t operand, int borrow) noexcept {
const auto data = BUS().DATA();
return MOS6502::sub_b(operand ,data, borrow);
}
uint8_t EightBit::Ricoh2A03::add(uint8_t operand, uint8_t data, int carry) noexcept {
uint8_t EightBit::Ricoh2A03::add(uint8_t operand, int carry) noexcept {
const auto data = BUS().DATA();
return MOS6502::add_b(operand, data, carry);
}

2
Z80/inc/Z80.h
View File

@ -89,7 +89,7 @@ namespace EightBit {
Signal<EventArgs> WritingIO;
Signal<EventArgs> WrittenIO;
int execute() noexcept final;
void execute() noexcept final;
int step() noexcept final;
[[nodiscard]] const register16_t& AF() const noexcept final;

12
Z80/src/Z80.cpp
View File

@ -601,9 +601,9 @@ uint8_t EightBit::Z80::fetchOpCode() noexcept {
const auto halted = lowered(HALT());
returned = IntelProcessor::memoryRead(PC());
if (UNLIKELY(halted))
returned = 0; // NOP
else
PC()++;
returned = 0; // NOP
else
PC()++;
}
BUS().ADDRESS() = { REFRESH(), IV() };
{
@ -778,10 +778,11 @@ int EightBit::Z80::step() noexcept {
IntelProcessor::execute(fetchOpCode());
}
ExecutedInstruction.fire(*this);
ASSUME(cycles() > 0);
return cycles();
}
int EightBit::Z80::execute() noexcept {
void EightBit::Z80::execute() noexcept {
const auto& decoded = getDecodedOpcode(opcode());
@ -798,9 +799,6 @@ int EightBit::Z80::execute() noexcept {
executeED(x, y, z, p, q);
else
executeOther(x, y, z, p, q);
ASSUME(cycles() > 0);
return cycles();
}
void EightBit::Z80::executeCB(const int x, const int y, const int z) noexcept {

4
inc/Processor.h
View File

@ -29,8 +29,8 @@ namespace EightBit {
int run(int limit) noexcept;
virtual int step() noexcept = 0;
virtual int execute() noexcept = 0;
int execute(uint8_t value) noexcept;
virtual void execute() noexcept = 0;
void execute(uint8_t value) noexcept;
[[nodiscard]] virtual register16_t peekWord(register16_t address) noexcept = 0;
virtual void pokeWord(register16_t address, register16_t value) noexcept = 0;

4
src/Processor.cpp
View File

@ -109,9 +109,9 @@ int EightBit::Processor::run(const int limit) noexcept {
return current;
}
int EightBit::Processor::execute(const uint8_t value) noexcept {
void EightBit::Processor::execute(const uint8_t value) noexcept {
opcode() = value;
return execute();
execute();
}
void EightBit::Processor::jump(const register16_t destination) noexcept {