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EightBit
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Author SHA1 Message Date
Adrian Conlon 739ce39360 Remove unused variable 2024-03-16 14:23:50 +00:00
Adrian Conlon 1c2b116a42 Start using "base" as means to access base-class. 2024-03-16 14:23:05 +00:00
Adrian Conlon f19e67875e More addressing / read tidying 2024-03-16 14:19:28 +00:00
11 changed files with 143 additions and 164 deletions
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1
M6502/HarteTest_6502/checker_t.cpp
View File

@ -218,7 +218,6 @@ void checker_t::check(test_t test) {
runner().raisePOWER();
initialiseState(test);
const auto pc = cpu.PC().word;
const auto start_opcode = runner().peek(pc);
m_cycles = cpu.step();
runner().lowerPOWER();

79
M6502/inc/mos6502.h
View File

@ -24,9 +24,9 @@ namespace EightBit {
public:
enum StatusBits {
NF = Bit7, // Negative
VF = Bit6, // Overflow
RF = Bit5, // reserved
BF = Bit4, // Brk
VF = Bit6, // Overflow
RF = Bit5, // reserved
BF = Bit4, // Brk
DF = Bit3, // D (use BCD for arithmetic)
IF = Bit2, // I (IRQ disable)
ZF = Bit1, // Zero
@ -58,21 +58,21 @@ namespace EightBit {
// Instructions with BCD effects
void sbc() noexcept;
[[nodiscard]] virtual uint8_t sub(uint8_t operand, int borrow = 0) noexcept;
[[nodiscard]] void sbc() noexcept;
[[nodiscard]] uint8_t sub_b(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
[[nodiscard]] uint8_t sub_d(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
void adc() noexcept;
[[nodiscard]] virtual uint8_t add(uint8_t operand, int carry = 0) noexcept;
[[nodiscard]] void adc() noexcept;
[[nodiscard]] uint8_t add_b(uint8_t operand, uint8_t data, int carry) noexcept;
[[nodiscard]] uint8_t add_d(uint8_t operand, uint8_t data, int carry) noexcept;
// Undocumented compound instructions (with BCD effects)
virtual void arr() noexcept;
virtual void arr_b(uint8_t value) noexcept;
virtual void arr_d(uint8_t value) noexcept;
void arr_b(uint8_t value) noexcept;
void arr_d(uint8_t value) noexcept;
private:
const uint8_t IRQvector = 0xfe; // IRQ vector
@ -105,19 +105,23 @@ namespace EightBit {
// Addressing modes
void Address_Immediate() noexcept { BUS().ADDRESS() = PC()++; }
constexpr void noteUnfixedPage() noexcept { m_unfixed_page = BUS().ADDRESS().high; }
constexpr void Address_Immediate() noexcept { BUS().ADDRESS() = PC()++; }
void Address_Absolute() noexcept { BUS().ADDRESS() = fetchWord(); }
void Address_ZeroPage() noexcept { BUS().ADDRESS() = register16_t(fetchByte(), 0); }
void Address_ZeroPageIndirect() noexcept;
void Address_Indirect() noexcept;
void Address_ZeroPageX() noexcept;
void Address_ZeroPageY() noexcept;
void Address_AbsoluteX() noexcept;
void Address_AbsoluteY() noexcept;
void Address_IndexedIndirectX() noexcept;
void Address_IndirectIndexedY() noexcept;
void Address_ZeroPageIndirect() noexcept { Address_ZeroPage(); BUS().ADDRESS() = getWordPaged(); }
void Address_Indirect() noexcept { Address_Absolute(); BUS().ADDRESS() = getWordPaged(); }
void Address_ZeroPageWithIndex(uint8_t index) noexcept { AM_ZeroPage(); BUS().ADDRESS().low += index; }
void Address_ZeroPageX() noexcept { Address_ZeroPageWithIndex(X()); }
void Address_ZeroPageY() noexcept { Address_ZeroPageWithIndex(Y()); }
void Address_AbsoluteWithIndex(uint8_t index) noexcept { Address_Absolute(); noteUnfixedPage(); BUS().ADDRESS() += index; }
void Address_AbsoluteX() noexcept { Address_AbsoluteWithIndex(X()); }
void Address_AbsoluteY() noexcept { Address_AbsoluteWithIndex(Y()); }
void Address_IndexedIndirectX() noexcept { Address_ZeroPageX(); BUS().ADDRESS() = getWordPaged(); }
void Address_IndirectIndexedY() noexcept { Address_ZeroPageIndirect(); noteUnfixedPage(); BUS().ADDRESS() += Y(); }
// Addressing modes, read
// Addressing modes, with read
void AM_Immediate() noexcept { Address_Immediate(); memoryRead(); }
void AM_Absolute() noexcept { Address_Absolute(); memoryRead(); }
@ -125,9 +129,9 @@ namespace EightBit {
void AM_ZeroPageX() noexcept { Address_ZeroPageX(); memoryRead(); }
void AM_ZeroPageY() noexcept { Address_ZeroPageY(); memoryRead(); }
void AM_IndexedIndirectX() noexcept { Address_IndexedIndirectX(); memoryRead(); }
void AM_AbsoluteX() noexcept { Address_AbsoluteX(); maybe_fixup(); memoryRead(); }
void AM_AbsoluteY() noexcept { Address_AbsoluteY(); maybe_fixup(); memoryRead(); }
void AM_IndirectIndexedY() noexcept { Address_IndirectIndexedY(); maybe_fixup(); memoryRead(); }
void AM_AbsoluteX() noexcept { Address_AbsoluteX(); maybe_fixupR(); }
void AM_AbsoluteY() noexcept { Address_AbsoluteY(); maybe_fixupR(); }
void AM_IndirectIndexedY() noexcept { Address_IndirectIndexedY(); maybe_fixupR(); }
// Flag checking
@ -173,9 +177,8 @@ namespace EightBit {
return data;
}
#define RMW(OPERATION) { \
const auto data = memoryRead(); \
const auto result = OPERATION(data); \
#define MW(OPERATION) { \
const auto result = OPERATION(BUS().DATA()); \
memoryWrite(); \
memoryWrite(result); \
}
@ -196,6 +199,9 @@ namespace EightBit {
BUS().ADDRESS().high = fixed_page;
}
void maybe_fixupR() noexcept { maybe_fixup(); memoryRead(); }
void fixupR() noexcept { fixup(); memoryRead(); }
// Status flag operations
constexpr static void set_flag(uint8_t& f, int which, int condition) noexcept { f = setBit(f, which, condition); }
@ -214,7 +220,7 @@ namespace EightBit {
// Instruction implementations
void andr() noexcept;
void bit(uint8_t operand) noexcept;
void bit() noexcept;
void cmp(uint8_t first) noexcept;
[[nodiscard]] uint8_t dec(uint8_t value) noexcept;
void eorr() noexcept;
@ -227,7 +233,7 @@ namespace EightBit {
void rts() noexcept;
[[nodiscard]] constexpr uint8_t asl(uint8_t value) noexcept {
set_flag(CF, value & Bit7);
set_flag(CF, value & NF);
return through(value << 1);
}
@ -237,7 +243,7 @@ namespace EightBit {
}
[[nodiscard]] constexpr uint8_t lsr(uint8_t value) noexcept {
set_flag(CF, value & Bit0);
set_flag(CF, value & CF);
return through(value >> 1);
}
@ -252,20 +258,23 @@ namespace EightBit {
void axs() noexcept;
void jam() noexcept;
void sha() noexcept { memoryWrite(A() & X() & (BUS().ADDRESS().high + 1)); }
void storeFixupEffect(uint8_t data) noexcept { memoryWrite(data & (BUS().ADDRESS().high + 1)); }
void sha() noexcept { storeFixupEffect(A() & X()); }
void sya() noexcept { storeFixupEffect(Y()); }
void sxa() noexcept { storeFixupEffect(X()); }
void tas() noexcept { S() = A() & X(); sha(); }
void las() noexcept { A() = X() = S() = through(memoryRead() & S()); }
void sya() noexcept { memoryWrite(Y() & (BUS().ADDRESS().high + 1)); }
void sxa() noexcept { memoryWrite(X() & (BUS().ADDRESS().high + 1)); }
void ane() noexcept { A() = through((A() | 0xee) & X() & BUS().DATA()); }
void atx() noexcept { A() = X() = through((A() | 0xee) & BUS().DATA()); }
void asr() noexcept { andr(); A() = lsr(A()); }
void isb() noexcept { RMW(inc); sbc(); }
void slo() noexcept { RMW(asl); orr(); }
void rla() noexcept { RMW(rol); andr(); }
void sre() noexcept { RMW(lsr); eorr(); }
void rra() noexcept { RMW(ror); adc(); }
void dcp() noexcept { RMW(dec); cmp(A()); }
void isb() noexcept { MW(inc); sbc(); }
void slo() noexcept { MW(asl); orr(); }
void rla() noexcept { MW(rol); andr(); }
void sre() noexcept { MW(lsr); eorr(); }
void rra() noexcept { MW(ror); adc(); }
void dcp() noexcept { MW(dec); cmp(A()); }
uint8_t m_x = 0; // index register X
uint8_t m_y = 0; // index register Y

211
M6502/src/mos6502.cpp
View File

@ -115,13 +115,13 @@ void EightBit::MOS6502::interrupt() noexcept {
void EightBit::MOS6502::busWrite() noexcept {
tick();
lowerRW();
Processor::busWrite();
base::busWrite();
}
uint8_t EightBit::MOS6502::busRead() noexcept {
tick();
raiseRW();
return Processor::busRead();
return base::busRead();
}
//
@ -133,138 +133,138 @@ void EightBit::MOS6502::execute() noexcept {
case 0x00: swallow_fetch(); interrupt(); break; // BRK (implied)
case 0x01: AM_IndexedIndirectX(); orr(); break; // ORA (indexed indirect X)
case 0x02: jam(); break; // *JAM
case 0x03: Address_IndexedIndirectX(); slo(); break; // *SLO (indexed indirect X)
case 0x03: AM_IndexedIndirectX(); slo(); break; // *SLO (indexed indirect X)
case 0x04: AM_ZeroPage(); break; // *NOP (zero page)
case 0x05: AM_ZeroPage(); orr(); break; // ORA (zero page)
case 0x06: Address_ZeroPage(); RMW(asl); break; // ASL (zero page)
case 0x07: Address_ZeroPage(); slo(); break; // *SLO (zero page)
case 0x06: AM_ZeroPage(); MW(asl); break; // ASL (zero page)
case 0x07: AM_ZeroPage(); slo(); break; // *SLO (zero page)
case 0x08: swallow(); php(); break; // PHP (implied)
case 0x09: AM_Immediate(); orr(); break; // ORA (immediate)
case 0x0a: swallow(); A() = asl(A()); break; // ASL A (implied)
case 0x0b: AM_Immediate(); anc(); break; // *ANC (immediate)
case 0x0c: Address_Absolute(); break; // *NOP (absolute)
case 0x0d: AM_Absolute(); orr(); break; // ORA (absolute)
case 0x0e: Address_Absolute(); RMW(asl); break; // ASL (absolute)
case 0x0f: Address_Absolute(); slo(); break; // *SLO (absolute)
case 0x0e: AM_Absolute(); MW(asl); break; // ASL (absolute)
case 0x0f: AM_Absolute(); slo(); break; // *SLO (absolute)
case 0x10: branch(negative() == 0); break; // BPL (relative)
case 0x11: AM_IndirectIndexedY(); orr(); break; // ORA (indirect indexed Y)
case 0x12: jam(); break; // *JAM
case 0x13: Address_IndirectIndexedY(); fixup(); slo(); break; // *SLO (indirect indexed Y)
case 0x13: Address_IndirectIndexedY(); fixupR(); slo(); break; // *SLO (indirect indexed Y)
case 0x14: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x15: AM_ZeroPageX(); orr(); break; // ORA (zero page, X)
case 0x16: Address_ZeroPageX(); RMW(asl); break; // ASL (zero page, X)
case 0x17: Address_ZeroPageX(); slo(); break; // *SLO (zero page, X)
case 0x16: AM_ZeroPageX(); MW(asl); break; // ASL (zero page, X)
case 0x17: AM_ZeroPageX(); slo(); break; // *SLO (zero page, X)
case 0x18: swallow(); reset_flag(CF); break; // CLC (implied)
case 0x19: AM_AbsoluteY(); orr(); break; // ORA (absolute, Y)
case 0x1a: swallow(); break; // *NOP (implied)
case 0x1b: Address_AbsoluteY(); fixup(); slo(); break; // *SLO (absolute, Y)
case 0x1b: Address_AbsoluteY(); fixupR(); slo(); break; // *SLO (absolute, Y)
case 0x1c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x1d: AM_AbsoluteX(); orr(); break; // ORA (absolute, X)
case 0x1e: Address_AbsoluteX(); fixup(); RMW(asl); break; // ASL (absolute, X)
case 0x1f: Address_AbsoluteX(); fixup(); slo(); break; // *SLO (absolute, X)
case 0x1e: Address_AbsoluteX(); fixupR(); MW(asl); break; // ASL (absolute, X)
case 0x1f: Address_AbsoluteX(); fixupR(); slo(); break; // *SLO (absolute, X)
case 0x20: jsr(); break; // JSR (absolute)
case 0x21: AM_IndexedIndirectX(); andr(); break; // AND (indexed indirect X)
case 0x22: jam(); break; // *JAM
case 0x23: Address_IndexedIndirectX(); rla();; break; // *RLA (indexed indirect X)
case 0x24: AM_ZeroPage(); bit(A()); break; // BIT (zero page)
case 0x23: AM_IndexedIndirectX(); rla();; break; // *RLA (indexed indirect X)
case 0x24: AM_ZeroPage(); bit(); break; // BIT (zero page)
case 0x25: AM_ZeroPage(); andr(); break; // AND (zero page)
case 0x26: Address_ZeroPage(); RMW(rol); break; // ROL (zero page)
case 0x27: Address_ZeroPage(); rla();; break; // *RLA (zero page)
case 0x26: AM_ZeroPage(); MW(rol); break; // ROL (zero page)
case 0x27: AM_ZeroPage(); rla();; break; // *RLA (zero page)
case 0x28: swallow(); plp(); break; // PLP (implied)
case 0x29: AM_Immediate(); andr(); break; // AND (immediate)
case 0x2a: swallow(); A() = rol(A()); break; // ROL A (implied)
case 0x2b: AM_Immediate(); anc(); break; // *ANC (immediate)
case 0x2c: AM_Absolute(); bit(A()); break; // BIT (absolute)
case 0x2c: AM_Absolute(); bit(); break; // BIT (absolute)
case 0x2d: AM_Absolute(); andr(); break; // AND (absolute)
case 0x2e: Address_Absolute(); RMW(rol); break; // ROL (absolute)
case 0x2f: Address_Absolute(); rla();; break; // *RLA (absolute)
case 0x2e: AM_Absolute(); MW(rol); break; // ROL (absolute)
case 0x2f: AM_Absolute(); rla();; break; // *RLA (absolute)
case 0x30: branch(negative()); break; // BMI (relative)
case 0x31: AM_IndirectIndexedY(); andr(); break; // AND (indirect indexed Y)
case 0x32: jam(); break; // *JAM
case 0x33: Address_IndirectIndexedY(); fixup(); rla();; break; // *RLA (indirect indexed Y)
case 0x33: Address_IndirectIndexedY(); fixupR(); rla();; break; // *RLA (indirect indexed Y)
case 0x34: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x35: AM_ZeroPageX(); andr(); break; // AND (zero page, X)
case 0x36: Address_ZeroPageX(); RMW(rol); break; // ROL (zero page, X)
case 0x37: Address_ZeroPageX(); rla();; break; // *RLA (zero page, X)
case 0x36: AM_ZeroPageX(); MW(rol); break; // ROL (zero page, X)
case 0x37: AM_ZeroPageX(); rla();; break; // *RLA (zero page, X)
case 0x38: swallow(); set_flag(CF); break; // SEC (implied)
case 0x39: AM_AbsoluteY(); andr(); break; // AND (absolute, Y)
case 0x3a: swallow(); break; // *NOP (implied)
case 0x3b: Address_AbsoluteY(); fixup(); rla();; break; // *RLA (absolute, Y)
case 0x3b: Address_AbsoluteY(); fixupR(); rla();; break; // *RLA (absolute, Y)
case 0x3c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x3d: AM_AbsoluteX(); andr(); break; // AND (absolute, X)
case 0x3e: Address_AbsoluteX(); fixup(); RMW(rol); break; // ROL (absolute, X)
case 0x3f: Address_AbsoluteX(); fixup(); rla();; break; // *RLA (absolute, X)
case 0x3e: Address_AbsoluteX(); fixupR(); MW(rol); break; // ROL (absolute, X)
case 0x3f: Address_AbsoluteX(); fixupR(); rla();; break; // *RLA (absolute, X)
case 0x40: swallow(); rti(); break; // RTI (implied)
case 0x41: AM_IndexedIndirectX(); eorr(); break; // EOR (indexed indirect X)
case 0x42: jam(); break; // *JAM
case 0x43: Address_IndexedIndirectX(); sre(); break; // *SRE (indexed indirect X)
case 0x43: AM_IndexedIndirectX(); sre(); break; // *SRE (indexed indirect X)
case 0x44: AM_ZeroPage(); break; // *NOP (zero page)
case 0x45: AM_ZeroPage(); eorr(); break; // EOR (zero page)
case 0x46: Address_ZeroPage(); RMW(lsr); break; // LSR (zero page)
case 0x47: Address_ZeroPage(); sre(); break; // *SRE (zero page)
case 0x46: AM_ZeroPage(); MW(lsr); break; // LSR (zero page)
case 0x47: AM_ZeroPage(); sre(); break; // *SRE (zero page)
case 0x48: swallow(); push(A()); break; // PHA (implied)
case 0x49: AM_Immediate(); eorr(); break; // EOR (immediate)
case 0x4a: swallow(); A() = lsr(A()); break; // LSR A (implied)
case 0x4b: AM_Immediate(); andr(); A() = lsr(A()); break; // *ASR (immediate)
case 0x4b: AM_Immediate(); asr(); break; // *ASR (immediate)
case 0x4c: Address_Absolute(); jump(BUS().ADDRESS()); break; // JMP (absolute)
case 0x4d: AM_Absolute(); eorr(); break; // EOR (absolute)
case 0x4e: Address_Absolute(); RMW(lsr); break; // LSR (absolute)
case 0x4f: Address_Absolute(); sre(); break; // *SRE (absolute)
case 0x4e: AM_Absolute(); MW(lsr); break; // LSR (absolute)
case 0x4f: AM_Absolute(); sre(); break; // *SRE (absolute)
case 0x50: branch(overflow() == 0); break; // BVC (relative)
case 0x51: AM_IndirectIndexedY(); eorr(); break; // EOR (indirect indexed Y)
case 0x52: jam(); break; // *JAM
case 0x53: Address_IndirectIndexedY(); fixup(); sre(); break; // *SRE (indirect indexed Y)
case 0x53: Address_IndirectIndexedY(); fixupR(); sre(); break; // *SRE (indirect indexed Y)
case 0x54: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x55: AM_ZeroPageX(); eorr(); break; // EOR (zero page, X)
case 0x56: Address_ZeroPageX(); RMW(lsr); break; // LSR (zero page, X)
case 0x57: Address_ZeroPageX(); sre(); break; // *SRE (zero page, X)
case 0x56: AM_ZeroPageX(); MW(lsr); break; // LSR (zero page, X)
case 0x57: AM_ZeroPageX(); sre(); break; // *SRE (zero page, X)
case 0x58: swallow(); reset_flag(IF); break; // CLI (implied)
case 0x59: AM_AbsoluteY(); eorr(); break; // EOR (absolute, Y)
case 0x5a: swallow(); break; // *NOP (implied)
case 0x5b: Address_AbsoluteY(); fixup(); sre(); break; // *SRE (absolute, Y)
case 0x5b: Address_AbsoluteY(); fixupR(); sre(); break; // *SRE (absolute, Y)
case 0x5c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x5d: AM_AbsoluteX(); eorr(); break; // EOR (absolute, X)
case 0x5e: Address_AbsoluteX(); fixup(); RMW(lsr); break; // LSR (absolute, X)
case 0x5f: Address_AbsoluteX(); fixup(); sre(); break; // *SRE (absolute, X)
case 0x5e: Address_AbsoluteX(); fixupR(); MW(lsr); break; // LSR (absolute, X)
case 0x5f: Address_AbsoluteX(); fixupR(); sre(); break; // *SRE (absolute, X)
case 0x60: swallow(); rts(); break; // RTS (implied)
case 0x61: AM_IndexedIndirectX(); adc(); break; // ADC (indexed indirect X)
case 0x62: jam(); break; // *JAM
case 0x63: Address_IndexedIndirectX(); rra(); break; // *RRA (indexed indirect X)
case 0x63: AM_IndexedIndirectX(); rra(); break; // *RRA (indexed indirect X)
case 0x64: AM_ZeroPage(); break; // *NOP (zero page)
case 0x65: AM_ZeroPage(); adc(); break; // ADC (zero page)
case 0x66: Address_ZeroPage(); RMW(ror); break; // ROR (zero page)
case 0x67: Address_ZeroPage(); rra(); break; // *RRA (zero page)
case 0x66: AM_ZeroPage(); MW(ror); break; // ROR (zero page)
case 0x67: AM_ZeroPage(); rra(); break; // *RRA (zero page)
case 0x68: swallow(); swallow_stack(); A() = through(pop()); break; // PLA (implied)
case 0x69: AM_Immediate(); adc(); break; // ADC (immediate)
case 0x6a: swallow(); A() = ror(A()); break; // ROR A (implied)
case 0x6b: AM_Immediate(); arr(); break; // *ARR (immediate)
case 0x6c: Address_Indirect(); jump(BUS().ADDRESS()); break; // JMP (indirect)
case 0x6d: AM_Absolute(); adc(); break; // ADC (absolute)
case 0x6e: Address_Absolute(); RMW(ror); break; // ROR (absolute)
case 0x6f: Address_Absolute(); rra(); break; // *RRA (absolute)
case 0x6e: AM_Absolute(); MW(ror); break; // ROR (absolute)
case 0x6f: AM_Absolute(); rra(); break; // *RRA (absolute)
case 0x70: branch(overflow()); break; // BVS (relative)
case 0x71: AM_IndirectIndexedY(); adc(); break; // ADC (indirect indexed Y)
case 0x72: jam(); break; // *JAM
case 0x73: Address_IndirectIndexedY(); fixup(); rra(); break; // *RRA (indirect indexed Y)
case 0x73: Address_IndirectIndexedY(); fixupR(); rra(); break; // *RRA (indirect indexed Y)
case 0x74: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x75: AM_ZeroPageX(); adc(); break; // ADC (zero page, X)
case 0x76: Address_ZeroPageX(); RMW(ror); break; // ROR (zero page, X)
case 0x77: Address_ZeroPageX(); rra(); break; // *RRA (zero page, X)
case 0x76: AM_ZeroPageX(); MW(ror); break; // ROR (zero page, X)
case 0x77: AM_ZeroPageX(); rra(); break; // *RRA (zero page, X)
case 0x78: swallow(); set_flag(IF); break; // SEI (implied)
case 0x79: AM_AbsoluteY(); adc(); break; // ADC (absolute, Y)
case 0x7a: swallow(); break; // *NOP (implied)
case 0x7b: Address_AbsoluteY(); fixup(); rra(); break; // *RRA (absolute, Y)
case 0x7b: Address_AbsoluteY(); fixupR(); rra(); break; // *RRA (absolute, Y)
case 0x7c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0x7d: AM_AbsoluteX(); adc(); break; // ADC (absolute, X)
case 0x7e: Address_AbsoluteX(); fixup(); RMW(ror); break; // ROR (absolute, X)
case 0x7f: Address_AbsoluteX(); fixup(); rra(); break; // *RRA (absolute, X)
case 0x7e: Address_AbsoluteX(); fixupR(); MW(ror); break; // ROR (absolute, X)
case 0x7f: Address_AbsoluteX(); fixupR(); rra(); break; // *RRA (absolute, X)
case 0x80: AM_Immediate(); break; // *NOP (immediate)
case 0x81: Address_IndexedIndirectX(); memoryWrite(A()); break; // STA (indexed indirect X)
@ -277,7 +277,7 @@ void EightBit::MOS6502::execute() noexcept {
case 0x88: swallow(); Y() = dec(Y()); break; // DEY (implied)
case 0x89: AM_Immediate(); break; // *NOP (immediate)
case 0x8a: swallow(); A() = through(X()); break; // TXA (implied)
case 0x8b: AM_Immediate(); ane(); break; // *ANE (immediate)
case 0x8b: AM_Immediate(); ane(); break; // *ANE (immediate)
case 0x8c: Address_Absolute(); memoryWrite(Y()); break; // STY (absolute)
case 0x8d: Address_Absolute(); memoryWrite(A()); break; // STA (absolute)
case 0x8e: Address_Absolute(); memoryWrite(X()); break; // STX (absolute)
@ -295,10 +295,10 @@ void EightBit::MOS6502::execute() noexcept {
case 0x99: Address_AbsoluteY(); fixup(); memoryWrite(A()); break; // STA (absolute, Y)
case 0x9a: swallow(); S() = X(); break; // TXS (implied)
case 0x9b: Address_AbsoluteY(); fixup(); tas(); break; // *TAS (absolute, Y)
case 0x9c: Address_AbsoluteX(); fixup(); sya(); break; // *SYA (absolute, X)
case 0x9c: Address_AbsoluteX(); fixup(); sya(); break; // *SYA (absolute, X)
case 0x9d: Address_AbsoluteX(); fixup(); memoryWrite(A()); break; // STA (absolute, X)
case 0x9e: Address_AbsoluteY(); fixup(); sxa(); break; // *SXA (absolute, Y)
case 0x9f: Address_AbsoluteY(); fixup(); sha(); break; // *SHA (absolute, Y)
case 0x9e: Address_AbsoluteY(); fixup(); sxa(); break; // *SXA (absolute, Y)
case 0x9f: Address_AbsoluteY(); fixup(); sha(); break; // *SHA (absolute, Y)
case 0xa0: AM_Immediate(); Y() = through(BUS().DATA()); break; // LDY (immediate)
case 0xa1: AM_IndexedIndirectX(); A() = through(BUS().DATA()); break; // LDA (indexed indirect X)
@ -335,72 +335,72 @@ void EightBit::MOS6502::execute() noexcept {
case 0xbf: AM_AbsoluteY(); A() = X() = through(BUS().DATA()); break; // *LAX (absolute, Y)
case 0xc0: AM_Immediate(); cmp(Y()); break; // CPY (immediate)
case 0xc1: AM_IndexedIndirectX(); cmp(A()); break; // CMP (indexed indirect X)
case 0xc1: AM_IndexedIndirectX(); cmp(A()); break; // CMP (indexed indirect X)
case 0xc2: AM_Immediate(); break; // *NOP (immediate)
case 0xc3: Address_IndexedIndirectX(); dcp(); break; // *DCP (indexed indirect X)
case 0xc4: AM_ZeroPage(); cmp(Y()); break; // CPY (zero page)
case 0xc5: AM_ZeroPage(); cmp(A()); break; // CMP (zero page)
case 0xc6: Address_ZeroPage(); RMW(dec); break; // DEC (zero page)
case 0xc7: Address_ZeroPage(); dcp(); break; // *DCP (zero page)
case 0xc3: AM_IndexedIndirectX(); dcp(); break; // *DCP (indexed indirect X)
case 0xc4: AM_ZeroPage(); cmp(Y()); break; // CPY (zero page)
case 0xc5: AM_ZeroPage(); cmp(A()); break; // CMP (zero page)
case 0xc6: AM_ZeroPage(); MW(dec); break; // DEC (zero page)
case 0xc7: AM_ZeroPage(); dcp(); break; // *DCP (zero page)
case 0xc8: swallow(); Y() = inc(Y()); break; // INY (implied)
case 0xc9: AM_Immediate(); cmp(A()); break; // CMP (immediate)
case 0xc9: AM_Immediate(); cmp(A()); break; // CMP (immediate)
case 0xca: swallow(); X() = dec(X()); break; // DEX (implied)
case 0xcb: AM_Immediate(); axs(); break; // *AXS (immediate)
case 0xcc: AM_Absolute(); cmp(Y()); break; // CPY (absolute)
case 0xcd: AM_Absolute(); cmp(A()); break; // CMP (absolute)
case 0xce: Address_Absolute(); RMW(dec); break; // DEC (absolute)
case 0xcf: Address_Absolute(); dcp(); break; // *DCP (absolute)
case 0xce: AM_Absolute(); MW(dec); break; // DEC (absolute)
case 0xcf: AM_Absolute(); dcp(); break; // *DCP (absolute)
case 0xd0: branch(zero() == 0); break; // BNE (relative)
case 0xd1: AM_IndirectIndexedY(); cmp(A()); break; // CMP (indirect indexed Y)
case 0xd2: jam(); break; // *JAM
case 0xd3: Address_IndirectIndexedY(); fixup(); dcp(); break; // *DCP (indirect indexed Y)
case 0xd3: Address_IndirectIndexedY(); fixupR(); dcp(); break; // *DCP (indirect indexed Y)
case 0xd4: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xd5: AM_ZeroPageX(); cmp(A()); break; // CMP (zero page, X)
case 0xd6: Address_ZeroPageX(); RMW(dec); break; // DEC (zero page, X)
case 0xd7: Address_ZeroPageX(); dcp(); break; // *DCP (zero page, X)
case 0xd6: AM_ZeroPageX(); MW(dec); break; // DEC (zero page, X)
case 0xd7: AM_ZeroPageX(); dcp(); break; // *DCP (zero page, X)
case 0xd8: swallow(); reset_flag(DF); break; // CLD (implied)
case 0xd9: AM_AbsoluteY(); cmp(A()); break; // CMP (absolute, Y)
case 0xda: swallow(); break; // *NOP (implied)
case 0xdb: Address_AbsoluteY(); fixup(); dcp(); break; // *DCP (absolute, Y)
case 0xdb: Address_AbsoluteY(); fixupR(); dcp(); break; // *DCP (absolute, Y)
case 0xdc: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0xdd: AM_AbsoluteX(); cmp(A()); break; // CMP (absolute, X)
case 0xde: Address_AbsoluteX(); fixup(); RMW(dec); break; // DEC (absolute, X)
case 0xdf: Address_AbsoluteX(); fixup(); dcp(); break; // *DCP (absolute, X)
case 0xde: Address_AbsoluteX(); fixupR(); MW(dec); break; // DEC (absolute, X)
case 0xdf: Address_AbsoluteX(); fixupR(); dcp(); break; // *DCP (absolute, X)
case 0xe0: AM_Immediate(); cmp(X()); break; // CPX (immediate)
case 0xe1: AM_IndexedIndirectX(); sbc(); break; // SBC (indexed indirect X)
case 0xe2: AM_Immediate(); break; // *NOP (immediate)
case 0xe3: Address_IndexedIndirectX(); isb(); break; // *ISB (indexed indirect X)
case 0xe3: AM_IndexedIndirectX(); isb(); break; // *ISB (indexed indirect X)
case 0xe4: AM_ZeroPage(); cmp(X()); break; // CPX (zero page)
case 0xe5: AM_ZeroPage(); sbc(); break; // SBC (zero page)
case 0xe6: Address_ZeroPage(); RMW(inc); break; // INC (zero page)
case 0xe7: Address_ZeroPage(); isb(); break; // *ISB (zero page)
case 0xe6: AM_ZeroPage(); MW(inc); break; // INC (zero page)
case 0xe7: AM_ZeroPage(); isb(); break; // *ISB (zero page)
case 0xe8: swallow(); X() = inc(X()); break; // INX (implied)
case 0xe9: AM_Immediate(); sbc(); break; // SBC (immediate)
case 0xea: swallow(); break; // NOP (implied)
case 0xeb: AM_Immediate(); sbc(); break; // *SBC (immediate)
case 0xec: AM_Absolute(); cmp(X()); break; // CPX (absolute)
case 0xed: AM_Absolute(); sbc(); break; // SBC (absolute)
case 0xee: Address_Absolute(); RMW(inc); break; // INC (absolute)
case 0xef: Address_Absolute(); isb(); break; // *ISB (absolute)
case 0xee: AM_Absolute(); MW(inc); break; // INC (absolute)
case 0xef: AM_Absolute(); isb(); break; // *ISB (absolute)
case 0xf0: branch(zero()); break; // BEQ (relative)
case 0xf1: AM_IndirectIndexedY(); sbc(); break; // SBC (indirect indexed Y)
case 0xf2: jam(); break; // *JAM
case 0xf3: Address_IndirectIndexedY(); fixup(); isb(); break; // *ISB (indirect indexed Y)
case 0xf3: Address_IndirectIndexedY(); fixupR(); isb(); break; // *ISB (indirect indexed Y)
case 0xf4: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xf5: AM_ZeroPageX(); sbc(); break; // SBC (zero page, X)
case 0xf6: Address_ZeroPageX(); RMW(inc); break; // INC (zero page, X)
case 0xf7: Address_ZeroPageX(); isb(); break; // *ISB (zero page, X)
case 0xf6: AM_ZeroPageX(); MW(inc); break; // INC (zero page, X)
case 0xf7: AM_ZeroPageX(); isb(); break; // *ISB (zero page, X)
case 0xf8: swallow(); set_flag(DF); break; // SED (implied)
case 0xf9: AM_AbsoluteY(); sbc(); break; // SBC (absolute, Y)
case 0xfa: swallow(); break; // *NOP (implied)
case 0xfb: Address_AbsoluteY(); fixup(); isb(); break; // *ISB (absolute, Y)
case 0xfb: Address_AbsoluteY(); fixupR(); isb(); break; // *ISB (absolute, Y)
case 0xfc: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
case 0xfd: AM_AbsoluteX(); sbc(); break; // SBC (absolute, X)
case 0xfe: Address_AbsoluteX(); fixup(); RMW(inc); break; // INC (absolute, X)
case 0xff: Address_AbsoluteX(); fixup(); isb(); break; // *ISB (absolute, X)
case 0xfe: Address_AbsoluteX(); fixupR(); MW(inc); break; // INC (absolute, X)
case 0xff: Address_AbsoluteX(); fixupR(); isb(); break; // *ISB (absolute, X)
}
}
@ -423,51 +423,6 @@ void EightBit::MOS6502::dummyPush(uint8_t value) noexcept {
////
void EightBit::MOS6502::Address_ZeroPageIndirect() noexcept {
Address_ZeroPage();
BUS().ADDRESS() = getWordPaged();
}
void EightBit::MOS6502::Address_Indirect() noexcept {
Address_Absolute();
BUS().ADDRESS() = getWordPaged();
}
void EightBit::MOS6502::Address_ZeroPageX() noexcept {
AM_ZeroPage();
BUS().ADDRESS().low += X();
}
void EightBit::MOS6502::Address_ZeroPageY() noexcept {
AM_ZeroPage();
BUS().ADDRESS().low += Y();
}
void EightBit::MOS6502::Address_AbsoluteX() noexcept {
Address_Absolute();
m_unfixed_page = BUS().ADDRESS().high;
BUS().ADDRESS() += X();
}
void EightBit::MOS6502::Address_AbsoluteY() noexcept {
Address_Absolute();
m_unfixed_page = BUS().ADDRESS().high;
BUS().ADDRESS() += Y();
}
void EightBit::MOS6502::Address_IndexedIndirectX() noexcept {
Address_ZeroPageX();
BUS().ADDRESS() = getWordPaged();
}
void EightBit::MOS6502::Address_IndirectIndexedY() noexcept {
Address_ZeroPageIndirect();
m_unfixed_page = BUS().ADDRESS().high;
BUS().ADDRESS() += Y();
}
////
void EightBit::MOS6502::branch(const int condition) noexcept {
const auto relative = int8_t(fetchByte());
if (condition) {
@ -565,10 +520,10 @@ void EightBit::MOS6502::andr() noexcept {
A() = through(A() & BUS().DATA());
}
void EightBit::MOS6502::bit(const uint8_t operand) noexcept {
void EightBit::MOS6502::bit() noexcept {
const auto data = BUS().DATA();
set_flag(VF, overflow(data));
adjustZero(operand & data);
adjustZero(A() & data);
adjustNegative(data);
}
@ -627,7 +582,7 @@ void EightBit::MOS6502::rts() noexcept {
void EightBit::MOS6502::anc() noexcept {
andr();
set_flag(CF, A() & Bit7);
set_flag(CF, A() & NF);
}
void EightBit::MOS6502::arr() noexcept {
@ -657,7 +612,7 @@ void EightBit::MOS6502::arr_d(const uint8_t value) noexcept {
void EightBit::MOS6502::arr_b(const uint8_t value) noexcept {
A() &= value;
A() = through((A() >> 1) | (carry() << 7));
set_flag(CF, A() & Bit6);
set_flag(CF, A() & VF);
set_flag(VF, overflow((A() ^ (A() << 1))));
}

2
inc/BigEndianProcessor.h
View File

@ -14,6 +14,8 @@ namespace EightBit {
void pokeWord(register16_t address, register16_t value) noexcept final;
protected:
using base = BigEndianProcessor;
BigEndianProcessor(Bus& memory) noexcept;
[[nodiscard]] register16_t getWord() override;

2
inc/Chip.h
View File

@ -70,6 +70,8 @@ namespace EightBit {
: Device(rhs) {}
protected:
using base = Chip;
Chip() noexcept = default;
};
}

2
inc/ClockedChip.h
View File

@ -22,6 +22,8 @@ namespace EightBit {
}
protected:
using base = ClockedChip;
ClockedChip() noexcept = default;
constexpr void resetCycles() noexcept { m_cycles = 0; }

2
inc/Device.h
View File

@ -114,6 +114,8 @@ namespace EightBit {
[[nodiscard]] constexpr bool powered() const noexcept { return raised(POWER()); }
protected:
using base = Device;
Device() noexcept {};
};
}

2
inc/IntelProcessor.h
View File

@ -80,6 +80,8 @@ namespace EightBit {
DECLARE_PIN_OUTPUT(HALT)
protected:
using base = IntelProcessor;
IntelProcessor(Bus& bus);
template<class T> [[nodiscard]] static constexpr uint8_t adjustSign(uint8_t f, const uint8_t value) noexcept {

2
inc/LittleEndianProcessor.h
View File

@ -14,6 +14,8 @@ namespace EightBit {
void pokeWord(register16_t address, register16_t value) noexcept final;
protected:
using base = LittleEndianProcessor;
LittleEndianProcessor(Bus& memory) noexcept;
[[nodiscard]] register16_t getWord() override;

2
inc/Processor.h
View File

@ -39,6 +39,8 @@ namespace EightBit {
DECLARE_PIN_INPUT(INT)
protected:
using base = Processor;
Processor(Bus& memory) noexcept;
[[nodiscard]] constexpr auto& opcode() noexcept { return m_opcode; }

2
inc/co_generator_t.h
View File

@ -15,6 +15,7 @@ public:
private:
using handle_t = std::coroutine_handle<promise_type>;
public:
class promise_type final {
private:
T value_;
@ -42,6 +43,7 @@ private:
[[nodiscard]] constexpr auto& exception() noexcept { return exception_; };
};
private:
handle_t h_;
private: