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b812554cb6 | ||
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fc30360165 | ||
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0a6ab11fbb |
9
.gitignore
vendored
9
.gitignore
vendored
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@ -49,3 +49,12 @@ packages/
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||||||
cpp_chip8
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cpp_chip8
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||||||
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||||||
src/state
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src/state
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||||||
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/config
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||||||
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/DawnCache
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||||||
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/GPUCache
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||||||
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/M6502/HarteTest_6502/e000
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||||||
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/M6502/HarteTest_6502/Intel® VTune™ Profiler Results/HarteTest_6502
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||||||
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*.advidb2
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||||||
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*.advixeproj
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||||||
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/M6502/test/Intel® VTune™ Profiler Results/test_M6502
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||||||
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/Z80/test/Intel® VTune™ Profiler Results
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@ -60,13 +60,12 @@ namespace EightBit {
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void sbc() noexcept;
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void sbc() noexcept;
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[[nodiscard]] virtual uint8_t sub(uint8_t operand, int borrow = 0) noexcept;
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[[nodiscard]] virtual uint8_t sub(uint8_t operand, int borrow = 0) noexcept;
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[[nodiscard]] uint8_t sub_b(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
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[[nodiscard]] uint8_t sub_b(uint8_t operand, int borrow = 0) noexcept;
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[[nodiscard]] uint8_t sub_d(uint8_t operand, uint8_t data, int borrow = 0) noexcept;
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[[nodiscard]] uint8_t sub_d(uint8_t operand, int borrow = 0) noexcept;
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void adc() noexcept;
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virtual void adc() noexcept;
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[[nodiscard]] virtual uint8_t add(uint8_t operand, int carry = 0) noexcept;
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void adc_b() noexcept;
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[[nodiscard]] uint8_t add_b(uint8_t operand, uint8_t data, int carry) noexcept;
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void adc_d() noexcept;
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[[nodiscard]] uint8_t add_d(uint8_t operand, uint8_t data, int carry) noexcept;
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// Undocumented compound instructions (with BCD effects)
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// Undocumented compound instructions (with BCD effects)
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@ -82,26 +81,47 @@ namespace EightBit {
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void handleNMI() noexcept;
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void handleNMI() noexcept;
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void handleSO() noexcept;
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void handleSO() noexcept;
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void interrupt() noexcept;
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enum interrupt_source_t { hardware, software };
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enum interrupt_type_t { reset, non_reset };
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void interrupt(uint8_t vector, interrupt_source_t source = hardware, interrupt_type_t type = non_reset) noexcept;
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constexpr void setStackAddress(uint8_t position) noexcept {
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constexpr void updateStack(uint8_t position) noexcept { BUS().ADDRESS() = { position, 1 }; }
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BUS().ADDRESS() = { position, 1 };
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constexpr void lowerStack() noexcept { updateStack(S()--); }
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}
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constexpr void raiseStack() noexcept { updateStack(++S()); }
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constexpr void pushDownStackAddress(uint8_t value) noexcept {
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BUS().DATA() = value;
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setStackAddress(S()--);
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}
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constexpr void popUpStackAddress() noexcept {
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setStackAddress(++S());
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}
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void push(uint8_t value) noexcept final;
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void push(uint8_t value) noexcept final;
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[[nodiscard]] uint8_t pop() noexcept final;
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[[nodiscard]] uint8_t pop() noexcept final;
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// Dummy stack push, used during RESET
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// Dummy stack push, used during RESET
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void dummyPush(uint8_t value) noexcept;
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void dummyPush() noexcept;
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uint8_t readFromBus() noexcept {
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raiseRW();
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return LittleEndianProcessor::busRead();
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}
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void writeToBus() noexcept {
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lowerRW();
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LittleEndianProcessor::busWrite();
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}
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// Read the opcode within the existing cycle
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void fetchInstruction() noexcept {
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// Instruction fetch beginning
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lowerSYNC();
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assert(cycles() == 1 && "An extra cycle has occurred");
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// Can't use fetchByte, since that would add an extra tick.
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Address_Immediate();
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opcode() = readFromBus();
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assert(cycles() == 1 && "BUS read has introduced stray cycles");
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// Instruction fetch has now completed
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raiseSYNC();
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}
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// Addressing modes
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// Addressing modes
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@ -109,7 +129,7 @@ namespace EightBit {
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constexpr void Address_Immediate() noexcept { BUS().ADDRESS() = PC()++; }
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constexpr void Address_Immediate() noexcept { BUS().ADDRESS() = PC()++; }
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void Address_Absolute() noexcept { BUS().ADDRESS() = fetchWord(); }
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void Address_Absolute() noexcept { BUS().ADDRESS() = fetchWord(); }
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void Address_ZeroPage() noexcept { BUS().ADDRESS() = register16_t(fetchByte(), 0); }
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void Address_ZeroPage() noexcept { BUS().ADDRESS() = { fetchByte(), 0 }; }
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void Address_ZeroPageIndirect() noexcept { Address_ZeroPage(); BUS().ADDRESS() = getWordPaged(); }
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void Address_ZeroPageIndirect() noexcept { Address_ZeroPage(); BUS().ADDRESS() = getWordPaged(); }
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void Address_Indirect() noexcept { Address_Absolute(); BUS().ADDRESS() = getWordPaged(); }
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void Address_Indirect() noexcept { Address_Absolute(); BUS().ADDRESS() = getWordPaged(); }
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void Address_ZeroPageWithIndex(uint8_t index) noexcept { AM_ZeroPage(); BUS().ADDRESS().low += index; }
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void Address_ZeroPageWithIndex(uint8_t index) noexcept { AM_ZeroPage(); BUS().ADDRESS().low += index; }
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@ -160,11 +180,15 @@ namespace EightBit {
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adjustNegative(datum);
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adjustNegative(datum);
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}
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}
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constexpr void adjustOverflow_add(uint8_t operand, uint8_t data, uint8_t intermediate) noexcept {
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constexpr void adjustOverflow_add(uint8_t operand) noexcept {
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const auto data = BUS().DATA();
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const auto intermediate = m_intermediate.low;
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set_flag(VF, negative(~(operand ^ data) & (operand ^ intermediate)));
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set_flag(VF, negative(~(operand ^ data) & (operand ^ intermediate)));
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}
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}
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constexpr void adjustOverflow_subtract(uint8_t operand, uint8_t data, uint8_t intermediate) noexcept {
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constexpr void adjustOverflow_subtract(uint8_t operand) noexcept {
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const auto data = BUS().DATA();
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const auto intermediate = m_intermediate.low;
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set_flag(VF, negative((operand ^ data) & (operand ^ intermediate)));
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set_flag(VF, negative((operand ^ data) & (operand ^ intermediate)));
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}
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}
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@ -177,7 +201,11 @@ namespace EightBit {
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return data;
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return data;
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}
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}
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#define MW(OPERATION) { \
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[[nodiscard]] constexpr auto through() noexcept {
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return through(BUS().DATA());
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}
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#define MW(OPERATION) { \
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const auto result = OPERATION(BUS().DATA()); \
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const auto result = OPERATION(BUS().DATA()); \
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memoryWrite(); \
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memoryWrite(); \
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memoryWrite(result); \
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memoryWrite(result); \
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@ -278,11 +306,6 @@ namespace EightBit {
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register16_t m_intermediate;
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register16_t m_intermediate;
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bool m_handlingRESET = false;
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bool m_handlingNMI = false;
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bool m_handlingINT = false;
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//uint8_t m_unfixed_page = 0;
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uint8_t m_fixed_page = 0;
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uint8_t m_fixed_page = 0;
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};
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};
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}
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}
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@ -34,14 +34,7 @@ int EightBit::MOS6502::step() noexcept {
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if (LIKELY(raised(RDY()))) {
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if (LIKELY(raised(RDY()))) {
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lowerSYNC(); // Instruction fetch beginning
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fetchInstruction();
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// Read the opcode within the existing cycle
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assert(cycles() == 1 && "An extra cycle has occurred");
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// Can't use fetchByte, since that would add an extra tick.
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raiseRW();
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opcode() = BUS().read(PC()++);
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assert(cycles() == 1 && "BUS read has introduced stray cycles");
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// Priority: RESET > NMI > INT
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// Priority: RESET > NMI > INT
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if (UNLIKELY(lowered(RESET())))
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if (UNLIKELY(lowered(RESET())))
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@ -50,12 +43,8 @@ int EightBit::MOS6502::step() noexcept {
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handleNMI();
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handleNMI();
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else if (UNLIKELY(lowered(INT()) && !interruptMasked()))
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else if (UNLIKELY(lowered(INT()) && !interruptMasked()))
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handleINT();
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handleINT();
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else
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// Instruction fetch has now completed
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execute();
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raiseSYNC();
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// Whatever opcode is available, execute it.
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execute();
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}
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}
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}
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}
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ExecutedInstruction.fire(*this);
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ExecutedInstruction.fire(*this);
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@ -73,55 +62,42 @@ void EightBit::MOS6502::handleSO() noexcept {
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void EightBit::MOS6502::handleRESET() noexcept {
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void EightBit::MOS6502::handleRESET() noexcept {
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raiseRESET();
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raiseRESET();
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m_handlingRESET = true;
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interrupt(RSTvector, hardware, reset);
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opcode() = 0x00; // BRK
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}
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}
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void EightBit::MOS6502::handleNMI() noexcept {
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void EightBit::MOS6502::handleNMI() noexcept {
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raiseNMI();
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raiseNMI();
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m_handlingNMI = true;
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interrupt(NMIvector);
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opcode() = 0x00; // BRK
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}
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}
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void EightBit::MOS6502::handleINT() noexcept {
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void EightBit::MOS6502::handleINT() noexcept {
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raiseINT();
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raiseINT();
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m_handlingINT = true;
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interrupt(IRQvector);
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opcode() = 0x00; // BRK
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}
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}
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void EightBit::MOS6502::interrupt() noexcept {
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void EightBit::MOS6502::interrupt(uint8_t vector, interrupt_source_t source, interrupt_type_t type) noexcept {
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const bool reset = m_handlingRESET;
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if (type == reset) {
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const bool nmi = m_handlingNMI;
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dummyPush();
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if (reset) {
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dummyPush();
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dummyPush(PC().high);
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dummyPush();
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dummyPush(PC().low);
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dummyPush(P());
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} else {
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} else {
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const bool irq = m_handlingINT;
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const bool hardware = nmi || irq || reset;
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const bool software = !hardware;
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pushWord(PC());
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pushWord(PC());
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push(P() | (software ? BF : 0));
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push(P() | (source == hardware ? 0 : BF));
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}
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}
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set_flag(IF); // Disable IRQ
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set_flag(IF); // Disable IRQ
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const uint8_t vector = reset ? RSTvector : (nmi ? NMIvector : IRQvector);
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jump(Processor::getWordPaged(0xff, vector));
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jump(Processor::getWordPaged(0xff, vector));
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m_handlingRESET = m_handlingNMI = m_handlingINT = false;
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}
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}
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//
|
//
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||||||
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|
||||||
void EightBit::MOS6502::busWrite() noexcept {
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void EightBit::MOS6502::busWrite() noexcept {
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tick();
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tick();
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lowerRW();
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writeToBus();
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LittleEndianProcessor::busWrite();
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}
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}
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uint8_t EightBit::MOS6502::busRead() noexcept {
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uint8_t EightBit::MOS6502::busRead() noexcept {
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tick();
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tick();
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raiseRW();
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return readFromBus();
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return LittleEndianProcessor::busRead();
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}
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}
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//
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//
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@ -130,7 +106,7 @@ void EightBit::MOS6502::execute() noexcept {
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switch (opcode()) {
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switch (opcode()) {
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case 0x00: swallow_fetch(); interrupt(); break; // BRK (implied)
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case 0x00: swallow_fetch(); interrupt(IRQvector, software); break; // BRK (implied)
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case 0x01: AM_IndexedIndirectX(); orr(); break; // ORA (indexed indirect X)
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case 0x01: AM_IndexedIndirectX(); orr(); break; // ORA (indexed indirect X)
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case 0x02: jam(); break; // *JAM
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case 0x02: jam(); break; // *JAM
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||||||
case 0x03: AM_IndexedIndirectX(); slo(); break; // *SLO (indexed indirect X)
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case 0x03: AM_IndexedIndirectX(); slo(); break; // *SLO (indexed indirect X)
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||||||
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@ -300,39 +276,39 @@ void EightBit::MOS6502::execute() noexcept {
|
||||||
case 0x9e: Address_AbsoluteY(); fixup(); sxa(); break; // *SXA (absolute, Y)
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case 0x9e: Address_AbsoluteY(); fixup(); sxa(); break; // *SXA (absolute, Y)
|
||||||
case 0x9f: Address_AbsoluteY(); fixup(); sha(); break; // *SHA (absolute, Y)
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case 0x9f: Address_AbsoluteY(); fixup(); sha(); break; // *SHA (absolute, Y)
|
||||||
|
|
||||||
case 0xa0: AM_Immediate(); Y() = through(BUS().DATA()); break; // LDY (immediate)
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case 0xa0: AM_Immediate(); Y() = through(); break; // LDY (immediate)
|
||||||
case 0xa1: AM_IndexedIndirectX(); A() = through(BUS().DATA()); break; // LDA (indexed indirect X)
|
case 0xa1: AM_IndexedIndirectX(); A() = through(); break; // LDA (indexed indirect X)
|
||||||
case 0xa2: AM_Immediate(); X() = through(BUS().DATA()); break; // LDX (immediate)
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case 0xa2: AM_Immediate(); X() = through(); break; // LDX (immediate)
|
||||||
case 0xa3: AM_IndexedIndirectX(); A() = X() = through(BUS().DATA()); break; // *LAX (indexed indirect X)
|
case 0xa3: AM_IndexedIndirectX(); A() = X() = through(); break; // *LAX (indexed indirect X)
|
||||||
case 0xa4: AM_ZeroPage(); Y() = through(BUS().DATA()); break; // LDY (zero page)
|
case 0xa4: AM_ZeroPage(); Y() = through(); break; // LDY (zero page)
|
||||||
case 0xa5: AM_ZeroPage(); A() = through(BUS().DATA()); break; // LDA (zero page)
|
case 0xa5: AM_ZeroPage(); A() = through(); break; // LDA (zero page)
|
||||||
case 0xa6: AM_ZeroPage(); X() = through(BUS().DATA()); break; // LDX (zero page)
|
case 0xa6: AM_ZeroPage(); X() = through(); break; // LDX (zero page)
|
||||||
case 0xa7: AM_ZeroPage(); A() = X() = through(BUS().DATA()); break; // *LAX (zero page)
|
case 0xa7: AM_ZeroPage(); A() = X() = through(); break; // *LAX (zero page)
|
||||||
case 0xa8: swallow(); Y() = through(A()); break; // TAY (implied)
|
case 0xa8: swallow(); Y() = through(A()); break; // TAY (implied)
|
||||||
case 0xa9: AM_Immediate(); A() = through(BUS().DATA()); break; // LDA (immediate)
|
case 0xa9: AM_Immediate(); A() = through(); break; // LDA (immediate)
|
||||||
case 0xaa: swallow(); X() = through(A()); break; // TAX (implied)
|
case 0xaa: swallow(); X() = through(A()); break; // TAX (implied)
|
||||||
case 0xab: AM_Immediate(); atx(); break; // *ATX (immediate)
|
case 0xab: AM_Immediate(); atx(); break; // *ATX (immediate)
|
||||||
case 0xac: AM_Absolute(); Y() = through(BUS().DATA()); break; // LDY (absolute)
|
case 0xac: AM_Absolute(); Y() = through(); break; // LDY (absolute)
|
||||||
case 0xad: AM_Absolute(); A() = through(BUS().DATA()); break; // LDA (absolute)
|
case 0xad: AM_Absolute(); A() = through(); break; // LDA (absolute)
|
||||||
case 0xae: AM_Absolute(); X() = through(BUS().DATA()); break; // LDX (absolute)
|
case 0xae: AM_Absolute(); X() = through(); break; // LDX (absolute)
|
||||||
case 0xaf: AM_Absolute(); A() = X() = through(BUS().DATA()); break; // *LAX (absolute)
|
case 0xaf: AM_Absolute(); A() = X() = through(); break; // *LAX (absolute)
|
||||||
|
|
||||||
case 0xb0: branch(carry()); break; // BCS (relative)
|
case 0xb0: branch(carry()); break; // BCS (relative)
|
||||||
case 0xb1: AM_IndirectIndexedY(); A() = through(BUS().DATA()); break; // LDA (indirect indexed Y)
|
case 0xb1: AM_IndirectIndexedY(); A() = through(); break; // LDA (indirect indexed Y)
|
||||||
case 0xb2: jam(); break; // *JAM
|
case 0xb2: jam(); break; // *JAM
|
||||||
case 0xb3: AM_IndirectIndexedY(); A() = X() = through(BUS().DATA()); break; // *LAX (indirect indexed Y)
|
case 0xb3: AM_IndirectIndexedY(); A() = X() = through(); break; // *LAX (indirect indexed Y)
|
||||||
case 0xb4: AM_ZeroPageX(); Y() = through(BUS().DATA()); break; // LDY (zero page, X)
|
case 0xb4: AM_ZeroPageX(); Y() = through(); break; // LDY (zero page, X)
|
||||||
case 0xb5: AM_ZeroPageX(); A() = through(BUS().DATA()); break; // LDA (zero page, X)
|
case 0xb5: AM_ZeroPageX(); A() = through(); break; // LDA (zero page, X)
|
||||||
case 0xb6: AM_ZeroPageY(); X() = through(BUS().DATA()); break; // LDX (zero page, Y)
|
case 0xb6: AM_ZeroPageY(); X() = through(); break; // LDX (zero page, Y)
|
||||||
case 0xb7: AM_ZeroPageY(); A() = X() = through(BUS().DATA()); break; // *LAX (zero page, Y)
|
case 0xb7: AM_ZeroPageY(); A() = X() = through(); break; // *LAX (zero page, Y)
|
||||||
case 0xb8: swallow(); reset_flag(VF); break; // CLV (implied)
|
case 0xb8: swallow(); reset_flag(VF); break; // CLV (implied)
|
||||||
case 0xb9: AM_AbsoluteY(); A() = through(BUS().DATA()); break; // LDA (absolute, Y)
|
case 0xb9: AM_AbsoluteY(); A() = through(); break; // LDA (absolute, Y)
|
||||||
case 0xba: swallow(); X() = through(S()); break; // TSX (implied)
|
case 0xba: swallow(); X() = through(S()); break; // TSX (implied)
|
||||||
case 0xbb: Address_AbsoluteY(); maybe_fixup(); las(); break; // *LAS (absolute, Y)
|
case 0xbb: Address_AbsoluteY(); maybe_fixup(); las(); break; // *LAS (absolute, Y)
|
||||||
case 0xbc: AM_AbsoluteX(); Y() = through(BUS().DATA()); break; // LDY (absolute, X)
|
case 0xbc: AM_AbsoluteX(); Y() = through(); break; // LDY (absolute, X)
|
||||||
case 0xbd: AM_AbsoluteX(); A() = through(BUS().DATA()); break; // LDA (absolute, X)
|
case 0xbd: AM_AbsoluteX(); A() = through(); break; // LDA (absolute, X)
|
||||||
case 0xbe: AM_AbsoluteY(); X() = through(BUS().DATA()); break; // LDX (absolute, Y)
|
case 0xbe: AM_AbsoluteY(); X() = through(); break; // LDX (absolute, Y)
|
||||||
case 0xbf: AM_AbsoluteY(); A() = X() = through(BUS().DATA()); break; // *LAX (absolute, Y)
|
case 0xbf: AM_AbsoluteY(); A() = X() = through(); break; // *LAX (absolute, Y)
|
||||||
|
|
||||||
case 0xc0: AM_Immediate(); cmp(Y()); break; // CPY (immediate)
|
case 0xc0: AM_Immediate(); cmp(Y()); break; // CPY (immediate)
|
||||||
case 0xc1: AM_IndexedIndirectX(); cmp(A()); break; // CMP (indexed indirect X)
|
case 0xc1: AM_IndexedIndirectX(); cmp(A()); break; // CMP (indexed indirect X)
|
||||||
|
@ -407,25 +383,26 @@ void EightBit::MOS6502::execute() noexcept {
|
||||||
////
|
////
|
||||||
|
|
||||||
void EightBit::MOS6502::push(uint8_t value) noexcept {
|
void EightBit::MOS6502::push(uint8_t value) noexcept {
|
||||||
pushDownStackAddress(value);
|
lowerStack();
|
||||||
memoryWrite();
|
memoryWrite(value);
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::pop() noexcept {
|
uint8_t EightBit::MOS6502::pop() noexcept {
|
||||||
popUpStackAddress();
|
raiseStack();
|
||||||
return memoryRead();
|
return memoryRead();
|
||||||
}
|
}
|
||||||
|
|
||||||
void EightBit::MOS6502::dummyPush(uint8_t value) noexcept {
|
void EightBit::MOS6502::dummyPush() noexcept {
|
||||||
pushDownStackAddress(value);
|
lowerStack();
|
||||||
tick(); // In place of the memory write
|
tick(); // In place of the memory write
|
||||||
}
|
}
|
||||||
|
|
||||||
////
|
////
|
||||||
|
|
||||||
void EightBit::MOS6502::branch(const int condition) noexcept {
|
void EightBit::MOS6502::branch(const int condition) noexcept {
|
||||||
const auto relative = int8_t(fetchByte());
|
AM_Immediate();
|
||||||
if (condition) {
|
if (condition) {
|
||||||
|
const auto relative = int8_t(BUS().DATA());
|
||||||
swallow();
|
swallow();
|
||||||
const auto address = PC() + relative;
|
const auto address = PC() + relative;
|
||||||
noteFixedAddress(address);
|
noteFixedAddress(address);
|
||||||
|
@ -441,23 +418,25 @@ void EightBit::MOS6502::sbc() noexcept {
|
||||||
const auto operand = A();
|
const auto operand = A();
|
||||||
A() = sub(operand, carry(~P()));
|
A() = sub(operand, carry(~P()));
|
||||||
|
|
||||||
const auto difference = m_intermediate;
|
adjustOverflow_subtract(operand);
|
||||||
adjustOverflow_subtract(operand, BUS().DATA(), difference.low);
|
adjustNZ(m_intermediate.low);
|
||||||
adjustNZ(difference.low);
|
reset_flag(CF, m_intermediate.high);
|
||||||
reset_flag(CF, difference.high);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::sub(const uint8_t operand, const int borrow) noexcept {
|
uint8_t EightBit::MOS6502::sub(const uint8_t operand, const int borrow) noexcept {
|
||||||
const auto data = BUS().DATA();
|
return decimal() ? sub_d(operand, borrow) : sub_b(operand, borrow);
|
||||||
return decimal() ? sub_d(operand, data, borrow) : sub_b(operand, data, borrow);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::sub_b(const uint8_t operand, const uint8_t data, const int borrow) noexcept {
|
uint8_t EightBit::MOS6502::sub_b(const uint8_t operand, const int borrow) noexcept {
|
||||||
|
const auto data = BUS().DATA();
|
||||||
m_intermediate.word = operand - data - borrow;
|
m_intermediate.word = operand - data - borrow;
|
||||||
return m_intermediate.low;
|
return m_intermediate.low;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::sub_d(const uint8_t operand, const uint8_t data, const int borrow) noexcept {
|
uint8_t EightBit::MOS6502::sub_d(const uint8_t operand, const int borrow) noexcept {
|
||||||
|
|
||||||
|
const auto data = BUS().DATA();
|
||||||
|
|
||||||
m_intermediate.word = operand - data - borrow;
|
m_intermediate.word = operand - data - borrow;
|
||||||
|
|
||||||
uint8_t low = lowNibble(operand) - lowNibble(data) - borrow;
|
uint8_t low = lowNibble(operand) - lowNibble(data) - borrow;
|
||||||
|
@ -474,29 +453,31 @@ uint8_t EightBit::MOS6502::sub_d(const uint8_t operand, const uint8_t data, cons
|
||||||
}
|
}
|
||||||
|
|
||||||
void EightBit::MOS6502::adc() noexcept {
|
void EightBit::MOS6502::adc() noexcept {
|
||||||
A() = add(A(), carry());
|
decimal() ? adc_d() : adc_b();
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::add(uint8_t operand, int carrying) noexcept {
|
void EightBit::MOS6502::adc_b() noexcept {
|
||||||
|
|
||||||
|
const auto operand = A();
|
||||||
const auto data = BUS().DATA();
|
const auto data = BUS().DATA();
|
||||||
return decimal() ? add_d(operand, data, carrying) : add_b(operand, data, carrying);
|
m_intermediate.word = operand + data + carry();
|
||||||
}
|
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::add_b(uint8_t operand, uint8_t data, int carrying) noexcept {
|
adjustOverflow_add(operand);
|
||||||
m_intermediate.word = operand + data + carrying;
|
|
||||||
|
|
||||||
adjustOverflow_add(operand, data, m_intermediate.low);
|
|
||||||
set_flag(CF, carry(m_intermediate.high));
|
set_flag(CF, carry(m_intermediate.high));
|
||||||
|
|
||||||
adjustNZ(m_intermediate.low);
|
adjustNZ(m_intermediate.low);
|
||||||
|
|
||||||
return m_intermediate.low;
|
A() = m_intermediate.low;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t EightBit::MOS6502::add_d(uint8_t operand, uint8_t data, int carry) noexcept {
|
void EightBit::MOS6502::adc_d() noexcept {
|
||||||
|
|
||||||
register16_t low = lowerNibble(operand) + lowerNibble(data) + carry;
|
const auto operand = A();
|
||||||
register16_t high = higherNibble(operand) + higherNibble(data);
|
const auto data = BUS().DATA();
|
||||||
|
|
||||||
|
register16_t low = lowerNibble(operand) + lowerNibble(data) + carry();
|
||||||
|
m_intermediate = higherNibble(operand) + higherNibble(data);
|
||||||
|
auto& high = m_intermediate;
|
||||||
|
|
||||||
adjustZero((low + high).low);
|
adjustZero((low + high).low);
|
||||||
|
|
||||||
|
@ -506,14 +487,14 @@ uint8_t EightBit::MOS6502::add_d(uint8_t operand, uint8_t data, int carry) noexc
|
||||||
}
|
}
|
||||||
|
|
||||||
adjustNegative(high.low);
|
adjustNegative(high.low);
|
||||||
adjustOverflow_add(operand, data, high.low);
|
adjustOverflow_add(operand);
|
||||||
|
|
||||||
if (high.word > 0x90)
|
if (high.word > 0x90)
|
||||||
high += 0x60;
|
high += 0x60;
|
||||||
|
|
||||||
set_flag(CF, high.high);
|
set_flag(CF, high.high);
|
||||||
|
|
||||||
return lowerNibble(low.low) | higherNibble(high.low);
|
A() = lowerNibble(low.low) | higherNibble(high.low);
|
||||||
}
|
}
|
||||||
|
|
||||||
void EightBit::MOS6502::andr() noexcept {
|
void EightBit::MOS6502::andr() noexcept {
|
||||||
|
@ -550,8 +531,7 @@ void EightBit::MOS6502::jsr() noexcept {
|
||||||
const auto low = fetchByte();
|
const auto low = fetchByte();
|
||||||
swallow_stack();
|
swallow_stack();
|
||||||
pushWord(PC());
|
pushWord(PC());
|
||||||
PC().high = fetchByte();
|
PC() = { low, fetchByte() };
|
||||||
PC().low = low;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void EightBit::MOS6502::orr() noexcept {
|
void EightBit::MOS6502::orr() noexcept {
|
||||||
|
@ -617,7 +597,7 @@ void EightBit::MOS6502::arr_b(const uint8_t value) noexcept {
|
||||||
}
|
}
|
||||||
|
|
||||||
void EightBit::MOS6502::axs() noexcept {
|
void EightBit::MOS6502::axs() noexcept {
|
||||||
X() = through(sub_b(A() & X(), BUS().DATA()));
|
X() = through(sub_b(A() & X()));
|
||||||
reset_flag(CF, m_intermediate.high);
|
reset_flag(CF, m_intermediate.high);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue
Block a user