555 lines
11 KiB
C++
555 lines
11 KiB
C++
#include "stdafx.h"
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#include "Disassembler.h"
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#include <sstream>
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#include <iomanip>
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#include <bitset>
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#include "Memory.h"
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#include "LR35902.h"
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#include "StatusFlags.h"
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Disassembler::Disassembler() {
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// Disable exceptions where too many format arguments are available
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m_formatter.exceptions(boost::io::all_error_bits ^ boost::io::too_many_args_bit);
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}
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std::string Disassembler::state(LR35902& cpu) {
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auto pc = cpu.getProgramCounter();
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auto sp = cpu.getStackPointer();
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auto a = cpu.A();
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auto f = cpu.F();
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auto b = cpu.B();
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auto c = cpu.C();
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auto d = cpu.D();
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auto e = cpu.E();
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auto h = cpu.H();
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auto l = cpu.L();
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std::ostringstream output;
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output
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<< "PC=" << hex(pc)
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<< " "
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<< "SP=" << hex(sp)
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<< " " << "A=" << hex(a) << " " << "F=" << flags(f)
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<< " " << "B=" << hex(b) << " " << "C=" << hex(c)
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<< " " << "D=" << hex(d) << " " << "E=" << hex(e)
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<< " " << "H=" << hex(h) << " " << "L=" << hex(l);
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return output.str();
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}
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std::string Disassembler::RP(int rp) const {
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switch (rp) {
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case 0:
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return "BC";
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case 1:
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return "DE";
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case 2:
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return "HL";
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case 3:
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return "SP";
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}
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throw std::logic_error("Unhandled register pair");
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}
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std::string Disassembler::RP2(int rp) const {
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switch (rp) {
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case 0:
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return "BC";
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case 1:
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return "DE";
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case 2:
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return "HL";
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case 3:
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return "AF";
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}
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throw std::logic_error("Unhandled register pair");
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}
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std::string Disassembler::R(int r) const {
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switch (r) {
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case 0:
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return "B";
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case 1:
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return "C";
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case 2:
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return "D";
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case 3:
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return "E";
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case 4:
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return "H";
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case 5:
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return "L";
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case 6:
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return "(HL)";
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case 7:
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return "A";
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}
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throw std::logic_error("Unhandled register");
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}
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std::string Disassembler::cc(int flag) {
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switch (flag) {
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case 0:
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return "NZ";
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case 1:
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return "Z";
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case 2:
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return "NC";
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case 3:
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return "C";
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case 4:
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return "PO";
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case 5:
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return "PE";
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case 6:
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return "P";
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case 7:
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return "M";
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}
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throw std::logic_error("Unhandled condition");
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}
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std::string Disassembler::alu(int which) {
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switch (which) {
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case 0: // ADD A,n
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return "ADD";
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case 1: // ADC
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return "ADC";
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case 2: // SUB n
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return "SUB";
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case 3: // SBC A,n
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return "SBC";
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case 4: // AND n
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return "AND";
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case 5: // XOR n
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return "XOR";
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case 6: // OR n
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return "OR";
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case 7: // CP n
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return "CP";
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}
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throw std::logic_error("Unhandled alu operation");
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}
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std::string Disassembler::disassemble(LR35902& cpu) {
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m_prefixCB = false;
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std::ostringstream output;
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disassemble(output, cpu, cpu.getProgramCounter());
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return output.str();
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}
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void Disassembler::disassemble(std::ostringstream& output, LR35902& cpu, uint16_t pc) {
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auto& memory = cpu.getMemory();
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auto opcode = memory.peek(pc);
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// hex opcode
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output << hex(opcode);
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auto x = (opcode & 0b11000000) >> 6;
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auto y = (opcode & 0b111000) >> 3;
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auto z = (opcode & 0b111);
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auto p = (y & 0b110) >> 1;
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auto q = (y & 1);
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auto immediate = memory.peek(pc + 1);
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auto absolute = cpu.getWord(pc + 1);
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auto displacement = (int8_t)immediate;
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auto relative = pc + displacement + 2;
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auto indexedImmediate = memory.peek(pc + 1);
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auto dumpCount = 0;
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std::string specification = "";
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if (m_prefixCB)
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disassembleCB(
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output, cpu, pc,
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specification, dumpCount,
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x, y, z, p, q);
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else
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disassembleOther(
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output, cpu, pc,
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specification, dumpCount,
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x, y, z, p, q);
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for (int i = 0; i < dumpCount; ++i)
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output << hex(memory.peek(pc + i + 1));
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output << '\t';
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m_formatter.parse(specification);
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output << m_formatter % (int)immediate % (int)absolute % relative % (int)displacement % indexedImmediate;
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}
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void Disassembler::disassembleCB(
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std::ostringstream& output,
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LR35902& cpu,
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uint16_t pc,
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std::string& specification,
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int& dumpCount,
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int x, int y, int z,
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int p, int q) {
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switch (x) {
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case 0: // rot[y] r[z]
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switch (y) {
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case 0:
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specification = "RLC " + R(z);
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break;
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case 1:
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specification = "RRC " + R(z);
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break;
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case 2:
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specification = "RL " + R(z);
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break;
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case 3:
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specification = "RR " + R(z);
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break;
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case 4:
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specification = "SLA " + R(z);
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break;
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case 5:
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specification = "SRA " + R(z);
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break;
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case 6:
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specification = "SWAP " + R(z);
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break;
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case 7:
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specification = "SRL " + R(z);
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break;
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}
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break;
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case 1: // BIT y, r[z]
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specification = "BIT " + decimal(y) + "," + R(z);
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break;
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case 2: // RES y, r[z]
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specification = "RES " + decimal(y) + "," + R(z);
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break;
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case 3: // SET y, r[z]
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specification = "SET " + decimal(y) + "," + R(z);
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break;
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}
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}
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void Disassembler::disassembleOther(
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std::ostringstream& output,
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LR35902& cpu,
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uint16_t pc,
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std::string& specification,
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int& dumpCount,
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int x, int y, int z,
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int p, int q) {
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switch (x) {
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case 0:
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switch (z) {
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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specification = "NOP";
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break;
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case 1: // GB: LD (nn),SP
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specification = "LD (%2$04XH),SP";
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dumpCount += 2;
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break;
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case 2: // GB: STOP
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specification = "STOP";
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break;
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case 3: // JR d
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specification = "JR %3$04XH";
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dumpCount++;
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break;
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default: // JR cc,d
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specification = "JR " + cc(y - 4) + ",%3$04XH";
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dumpCount++;
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q) {
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case 0: // LD rp,nn
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specification = "LD " + RP(p) + ",%2$04XH";
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dumpCount += 2;
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break;
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case 1: // ADD HL,rp
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specification = "ADD HL," + RP(p);
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q) {
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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specification = "LD (BC),A";
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break;
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case 1: // LD (DE),A
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specification = "LD (DE),A";
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break;
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case 2: // GB: LDI (HL),A
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specification = "LDI (HL),A";
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break;
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case 3: // GB: LDD (HL),A
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specification = "LDD (HL),A";
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break;
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}
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break;
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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specification = "LD A,(BC)";
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break;
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case 1: // LD A,(DE)
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specification = "LD A,(DE)";
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break;
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case 2: // GB: LDI A,(HL)
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specification = "LDI A,(HL)";
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break;
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case 3: // GB: LDD A,(HL)
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specification = "LDD A,(HL)";
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break;
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}
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break;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q) {
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case 0: // INC rp
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specification = "INC " + RP(p);
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break;
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case 1: // DEC rp
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specification = "DEC " + RP(p);
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break;
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}
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break;
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case 4: // 8-bit INC
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specification = "INC " + R(y);
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break;
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case 5: // 8-bit DEC
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specification = "DEC " + R(y);
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break;
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case 6: // 8-bit load immediate
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specification = "LD " + R(y) + ",%1$02XH";
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dumpCount++;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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case 0:
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specification = "RLCA";
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break;
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case 1:
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specification = "RRCA";
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break;
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case 2:
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specification = "RLA";
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break;
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case 3:
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specification = "RRA";
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break;
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case 4:
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specification = "DAA";
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break;
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case 5:
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specification = "CPL";
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break;
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case 6:
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specification = "SCF";
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break;
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case 7:
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specification = "CCF";
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break;
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}
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break;
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}
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break;
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case 1: // 8-bit loading
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if (z == 6 && y == 6) { // Exception (replaces LD (HL), (HL))
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specification = "HALT";
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} else {
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specification = "LD " + R(y) + "," + R(z);
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}
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break;
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case 2: // Operate on accumulator and register/memory location
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specification = alu(y) + " A," + R(z);
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break;
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case 3:
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switch (z) {
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case 0: // Conditional return
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switch (y) {
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case 0:
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case 1:
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case 2:
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case 3:
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specification = "RET " + cc(y);
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break;
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case 4:
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specification = "LD (FF00H+%1$02XH),A";
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dumpCount++;
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break;
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case 5:
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specification = "ADD SP,%3$04XH";
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dumpCount++;
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break;
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case 6:
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specification = "LD A,(FF00H+%1$02XH)";
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dumpCount++;
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break;
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case 7:
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specification = "LD HL,SP+%3$04XH";
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dumpCount++;
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break;
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}
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break;
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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specification = "POP " + RP2(p);
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break;
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case 1:
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switch (p) {
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case 0: // RET
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specification = "RET";
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break;
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case 1: // GB: RETI
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specification = "RETI";
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break;
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case 2: // JP (HL)
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specification = "JP (HL)";
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break;
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case 3: // LD SP,HL
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specification = "LD SP,Hl";
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break;
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}
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}
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break;
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case 2: // Conditional jump
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switch (y) {
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case 0:
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case 1:
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case 2:
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case 3:
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specification = "JP " + cc(y) + ",%2$04XH";
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dumpCount += 2;
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break;
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case 4:
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specification = "LD (FF00H+C),A";
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break;
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case 5:
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specification = "LD (%2$04XH),A";
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dumpCount += 2;
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break;
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case 6:
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specification = "LD A,(FF00H+C)";
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break;
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case 7:
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specification = "LD A,(%2$04XH)";
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dumpCount += 2;
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break;
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}
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break;
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case 3: // Assorted operations
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switch (y) {
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case 0: // JP nn
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specification = "JP %2$04XH";
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dumpCount += 2;
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break;
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case 1: // CB prefix
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m_prefixCB = true;
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disassemble(output, cpu, pc + 1);
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break;
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case 6: // DI
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specification = "DI";
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break;
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case 7: // EI
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specification = "EI";
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break;
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}
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break;
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case 4: // Conditional call: CALL cc[y], nn
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specification = "CALL " + cc(y) + ",%2$04XH";
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dumpCount += 2;
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break;
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case 5: // PUSH & various ops
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switch (q) {
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case 0: // PUSH rp2[p]
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specification = "PUSH " + RP2(p);
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break;
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case 1:
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switch (p) {
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case 0: // CALL nn
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specification = "CALL %2$04XH";
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dumpCount += 2;
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break;
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}
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}
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break;
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case 6: // Operate on accumulator and immediate operand: alu[y] n
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specification = alu(y) + " A,%1$02XH";
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dumpCount++;
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break;
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case 7: // Restart: RST y * 8
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specification = "RST " + hex((uint8_t)(y * 8)) + "H";
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break;
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}
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break;
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}
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}
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std::string Disassembler::flag(uint8_t value, int flag, const std::string& represents) {
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std::ostringstream output;
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output << (value & flag ? represents : "-");
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return output.str();
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}
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std::string Disassembler::flags(uint8_t value) {
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std::ostringstream output;
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output
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<< flag(value, LR35902::ZF, "Z")
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<< flag(value, LR35902::NF, "N")
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<< flag(value, LR35902::HC, "H")
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<< flag(value, LR35902::CF, "C")
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<< flag(value, Processor::Bit3, "+")
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<< flag(value, Processor::Bit2, "+")
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<< flag(value, Processor::Bit1, "+")
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<< flag(value, Processor::Bit0, "+");
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return output.str();
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}
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std::string Disassembler::hex(uint8_t value) {
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std::ostringstream output;
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output << std::hex << std::setw(2) << std::setfill('0') << (int)value;
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return output.str();
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}
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std::string Disassembler::hex(uint16_t value) {
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std::ostringstream output;
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output << std::hex << std::setw(4) << std::setfill('0') << (int)value;
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return output.str();
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}
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std::string Disassembler::binary(uint8_t value) {
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std::ostringstream output;
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output << std::bitset<8>(value);
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return output.str();
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}
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std::string Disassembler::decimal(uint8_t value) {
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std::ostringstream output;
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output << (int)value;
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return output.str();
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}
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std::string Disassembler::invalid(uint8_t value) {
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std::ostringstream output;
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output << "Invalid instruction: " << hex(value) << "(" << binary(value) << ")";
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return output.str();
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} |