912 lines
16 KiB
C++
912 lines
16 KiB
C++
#include "stdafx.h"
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#include "LR35902.h"
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// based on http://www.z80.info/decoding.htm
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// Half carry flag help from https://github.com/oubiwann/z80
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LR35902::LR35902(Bus& memory)
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: Processor(memory),
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m_ime(false),
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m_prefixCB(false) {
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}
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void LR35902::reset() {
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Processor::reset();
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setStackPointer(0xfffe);
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di();
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}
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void LR35902::initialise() {
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Processor::initialise();
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AF().word = 0xffff;
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BC().word = 0xffff;
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DE().word = 0xffff;
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HL().word = 0xffff;
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m_prefixCB = false;
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}
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void LR35902::di() {
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IME() = false;
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}
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void LR35902::ei() {
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IME() = true;
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}
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int LR35902::interrupt(uint8_t value) {
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di();
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restart(value);
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return 4;
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}
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void LR35902::adjustZero(uint8_t value) {
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clearFlag(ZF, value);
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}
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void LR35902::postIncrement(uint8_t value) {
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adjustZero(value);
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clearFlag(NF);
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clearFlag(HC, lowNibble(value));
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}
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void LR35902::postDecrement(uint8_t value) {
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adjustZero(value);
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setFlag(NF);
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clearFlag(HC, lowNibble(value + 1));
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}
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void LR35902::restart(uint8_t address) {
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pushWord(pc);
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pc = address;
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}
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void LR35902::jrConditional(int conditional) {
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auto offset = (int8_t)fetchByte();
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if (conditional) {
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pc += offset;
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cycles++;
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}
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}
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void LR35902::jrConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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jrConditional(!(F() & ZF));
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break;
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case 1: // Z
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jrConditional(F() & ZF);
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break;
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case 2: // NC
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jrConditional(!(F() & CF));
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break;
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case 3: // C
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jrConditional(F() & CF);
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break;
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case 4: // PO
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case 5: // PE
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case 6: // P
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case 7: // M
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cycles -= 2;
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break;
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}
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}
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void LR35902::jumpConditional(int conditional) {
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auto address = fetchWord();
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if (conditional) {
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pc = address;
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cycles++;
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}
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}
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void LR35902::jumpConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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jumpConditional(!(F() & ZF));
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break;
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case 1: // Z
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jumpConditional(F() & ZF);
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break;
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case 2: // NC
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jumpConditional(!(F() & CF));
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break;
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case 3: // C
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jumpConditional(F() & CF);
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break;
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case 4: // GB: LD (FF00 + C),A
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m_memory.set(0xff00 + C(), A());
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cycles--; // Giving 8 cycles
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break;
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case 5: // GB: LD (nn),A
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m_memory.set(fetchWord(), A());
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cycles++; // Giving 16 cycles
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break;
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case 6: // GB: LD A,(FF00 + C)
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A() = m_memory.get(0xff00 + C());
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cycles--; // 8 cycles
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break;
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case 7: // GB: LD A,(nn)
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A() = m_memory.get(fetchWord());
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cycles++; // Giving 16 cycles
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break;
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}
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}
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void LR35902::ret() {
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pc = popWord();
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}
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void LR35902::reti() {
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ret();
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ei();
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}
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void LR35902::returnConditional(int condition) {
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if (condition) {
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ret();
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cycles += 3;
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}
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}
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void LR35902::returnConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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returnConditional(!(F() & ZF));
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break;
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case 1: // Z
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returnConditional(F() & ZF);
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break;
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case 2: // NC
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returnConditional(!(F() & CF));
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break;
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case 3: // C
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returnConditional(F() & CF);
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break;
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case 4: // GB: LD (FF00 + n),A
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m_memory.set(0xff00 + fetchByte(), A());
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cycles++; // giving 12 cycles in total
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break;
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case 5: { // GB: ADD SP,dd
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auto before = sp;
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auto value = fetchByte();
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sp += (int8_t)value;
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clearFlag(ZF | NF);
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setFlag(CF, sp & Bit16);
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adjustHalfCarryAdd(Memory::highByte(before), value, Memory::highByte(sp));
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}
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cycles += 2; // 16 cycles
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break;
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case 6: // GB: LD A,(FF00 + n)
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A() = m_memory.get(0xff00 + fetchByte());
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cycles++; // 12 cycles
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break;
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case 7: { // GB: LD HL,SP + dd
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auto before = sp;
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auto value = fetchByte();
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uint16_t result = before + (int8_t)value;
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HL().word = result;
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clearFlag(ZF | NF);
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setFlag(CF, result & Bit16);
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adjustHalfCarryAdd(Memory::highByte(before), value, Memory::highByte(result));
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}
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cycles++; // 12 cycles
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break;
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}
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}
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void LR35902::call(uint16_t address) {
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pushWord(pc + 2);
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pc = address;
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}
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void LR35902::callConditional(uint16_t address, int condition) {
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if (condition) {
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call(address);
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cycles += 3;
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} else {
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pc += 2;
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}
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}
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void LR35902::callConditionalFlag(uint16_t address, int flag) {
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switch (flag) {
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case 0: // NZ
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callConditional(address, !(F() & ZF));
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break;
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case 1: // Z
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callConditional(address, F() & ZF);
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break;
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case 2: // NC
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callConditional(address, !(F() & CF));
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break;
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case 3: // C
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callConditional(address, F() & CF);
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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cycles -= 3; // removed from GB
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break;
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}
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}
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uint16_t LR35902::sbc(uint16_t value) {
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auto hl = RP(HL_IDX);
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auto high = Memory::highByte(hl);
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auto highValue = Memory::highByte(value);
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auto applyCarry = F() & CF;
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uint32_t result = (int)hl - (int)value;
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if (applyCarry)
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--result;
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auto highResult = Memory::highByte(result);
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adjustZero(result);
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adjustHalfCarrySub(high, highValue, highResult);
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setFlag(NF);
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setFlag(CF, result & Bit16);
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return result;
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}
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uint16_t LR35902::adc(uint16_t value) {
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auto hl = RP(HL_IDX);
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auto high = Memory::highByte(hl);
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auto highValue = Memory::highByte(value);
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auto applyCarry = F() & CF;
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uint32_t result = (int)hl + (int)value;
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if (applyCarry)
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++result;
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auto highResult = Memory::highByte(result);
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adjustZero(result);
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adjustHalfCarryAdd(high, highValue, highResult);
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clearFlag(NF);
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setFlag(CF, result & Bit16);
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return result;
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}
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uint16_t LR35902::add(uint16_t value) {
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auto hl = RP(HL_IDX);
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auto high = Memory::highByte(hl);
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auto highValue = Memory::highByte(value);
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uint32_t result = (int)hl + (int)value;
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auto highResult = Memory::highByte(result);
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clearFlag(NF);
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setFlag(CF, result & Bit16);
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adjustHalfCarryAdd(high, highValue, highResult);
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return result;
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}
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void LR35902::sub(uint8_t& operand, uint8_t value, bool carry) {
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auto before = operand;
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uint16_t result = before - value;
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if (carry && (F() & CF))
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--result;
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operand = Memory::lowByte(result);
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adjustZero(operand);
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adjustHalfCarrySub(before, value, result);
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setFlag(NF);
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setFlag(CF, result & Bit8);
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}
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void LR35902::sbc(uint8_t& operand, uint8_t value) {
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sub(operand, value, true);
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}
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void LR35902::sub(uint8_t& operand, uint8_t value) {
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sub(operand, value, false);
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}
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void LR35902::add(uint8_t& operand, uint8_t value, bool carry) {
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auto before = operand;
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uint16_t result = before + value;
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if (carry && (F() & CF))
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++result;
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operand = Memory::lowByte(result);
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adjustZero(operand);
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adjustHalfCarryAdd(before, value, result);
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clearFlag(NF);
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setFlag(CF, result & Bit8);
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}
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void LR35902::adc(uint8_t& operand, uint8_t value) {
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add(operand, value, true);
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}
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void LR35902::add(uint8_t& operand, uint8_t value) {
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add(operand, value, false);
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}
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//
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void LR35902::andr(uint8_t& operand, uint8_t value) {
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setFlag(HC);
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clearFlag(CF | NF);
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operand &= value;
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adjustZero(operand);
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}
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void LR35902::anda(uint8_t value) {
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andr(A(), value);
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}
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void LR35902::xora(uint8_t value) {
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clearFlag(HC | CF | NF);
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A() ^= value;
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adjustZero(A());
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}
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void LR35902::ora(uint8_t value) {
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clearFlag(HC | CF | NF);
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A() |= value;
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adjustZero(A());
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}
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void LR35902::compare(uint8_t value) {
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auto check = A();
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sub(check, value);
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}
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//
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void LR35902::rlc(uint8_t& operand) {
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auto carry = operand & Bit7;
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operand <<= 1;
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setFlag(CF, carry);
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carry ? operand |= Bit0 : operand &= ~Bit0;
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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void LR35902::rrc(uint8_t& operand) {
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auto carry = operand & Bit0;
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operand >>= 1;
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carry ? operand |= Bit7 : operand &= ~Bit7;
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setFlag(CF, carry);
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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void LR35902::rl(uint8_t& operand) {
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auto oldCarry = F() & CF;
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auto newCarry = operand & Bit7;
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operand <<= 1;
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oldCarry ? operand |= Bit0 : operand &= ~Bit0;
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setFlag(CF, newCarry);
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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void LR35902::rr(uint8_t& operand) {
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auto oldCarry = F() & CF;
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auto newCarry = operand & Bit0;
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operand >>= 1;
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operand |= oldCarry << 7;
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setFlag(CF, newCarry);
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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//
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void LR35902::sla(uint8_t& operand) {
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auto newCarry = operand & Bit7;
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operand <<= 1;
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setFlag(CF, newCarry);
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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void LR35902::sra(uint8_t& operand) {
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auto new7 = operand & Bit7;
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auto newCarry = operand & Bit0;
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operand >>= 1;
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operand |= new7;
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setFlag(CF, newCarry);
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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void LR35902::srl(uint8_t& operand) {
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auto newCarry = operand & Bit0;
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operand >>= 1;
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operand &= ~Bit7; // clear bit 7
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setFlag(CF, newCarry);
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clearFlag(NF | HC);
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adjustZero(operand);
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}
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//
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void LR35902::rlca() {
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rlc(A());
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}
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void LR35902::rrca() {
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rrc(A());
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}
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void LR35902::rla() {
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rl(A());
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}
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void LR35902::rra() {
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rr(A());
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}
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//
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void LR35902::bit(int n, uint8_t& operand) {
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auto carry = F() & CF;
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uint8_t discarded = operand;
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andr(discarded, 1 << n);
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setFlag(CF, carry);
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}
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void LR35902::res(int n, uint8_t& operand) {
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auto bit = 1 << n;
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operand &= ~bit;
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}
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void LR35902::set(int n, uint8_t& operand) {
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auto bit = 1 << n;
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operand |= bit;
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}
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//
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void LR35902::daa() {
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uint8_t a = A();
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auto lowAdjust = (F() & HC) | ((A() & 0xf) > 9);
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auto highAdjust = (F() & CF) | (A() > 0x99);
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if (F() & NF) {
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if (lowAdjust)
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a -= 6;
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if (highAdjust)
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a -= 0x60;
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} else {
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if (lowAdjust)
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a += 6;
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if (highAdjust)
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a += 0x60;
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}
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F() = (F() & (CF | NF)) | (A() > 0x99) | ((A() ^ a) & HC);
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adjustZero(a);
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A() = a;
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}
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void LR35902::cpl() {
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A() = ~A();
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setFlag(HC | NF);
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}
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void LR35902::scf() {
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setFlag(CF);
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clearFlag(HC | NF);
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}
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void LR35902::ccf() {
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auto carry = F() & CF;
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clearFlag(CF, carry);
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clearFlag(NF | HC);
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}
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void LR35902::swap(uint8_t& operand) {
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auto low = lowNibble(operand);
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auto high = highNibble(operand);
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operand = promoteNibble(low) | demoteNibble(high);
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adjustZero(operand);
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clearFlag(NF | HC | CF);
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}
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int LR35902::step() {
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ExecutingInstruction.fire(*this);
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m_prefixCB = false;
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return fetchExecute();
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}
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int LR35902::execute(uint8_t opcode) {
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auto x = (opcode & 0b11000000) >> 6;
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auto y = (opcode & 0b111000) >> 3;
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auto z = (opcode & 0b111);
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auto p = (y & 0b110) >> 1;
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auto q = (y & 1);
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cycles = 0;
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if (m_prefixCB)
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executeCB(x, y, z, p, q);
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else
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executeOther(x, y, z, p, q);
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if (cycles == 0)
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throw std::logic_error("Unhandled opcode");
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return cycles * 4;
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}
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void LR35902::executeCB(int x, int y, int z, int p, int q) {
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switch (x) {
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case 0: // rot[y] r[z]
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switch (y) {
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case 0:
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rlc(R(z));
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break;
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case 1:
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rrc(R(z));
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break;
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case 2:
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rl(R(z));
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break;
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case 3:
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rr(R(z));
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break;
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case 4:
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sla(R(z));
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break;
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case 5:
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sra(R(z));
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break;
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case 6:
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swap(R(z));
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break;
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case 7:
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srl(R(z));
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break;
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}
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adjustZero(R(z));
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cycles += 2;
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if (z == 6)
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cycles += 2;
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break;
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case 1: // BIT y, r[z]
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bit(y, R(z));
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cycles += 2;
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if (z == 6)
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cycles += 2;
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break;
|
|
case 2: // RES y, r[z]
|
|
res(y, R(z));
|
|
cycles += 2;
|
|
if (z == 6)
|
|
cycles += 2;
|
|
break;
|
|
case 3: // SET y, r[z]
|
|
set(y, R(z));
|
|
cycles += 2;
|
|
if (z == 6)
|
|
cycles += 2;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void LR35902::executeOther(int x, int y, int z, int p, int q) {
|
|
switch (x) {
|
|
case 0:
|
|
switch (z) {
|
|
case 0: // Relative jumps and assorted ops
|
|
switch (y) {
|
|
case 0: // NOP
|
|
cycles++;
|
|
break;
|
|
case 1: // GB: LD (nn),SP
|
|
m_memory.setWord(fetchWord(), sp);
|
|
cycles += 5;
|
|
break;
|
|
case 2: // GB: STOP
|
|
stop();
|
|
cycles++;
|
|
break;
|
|
case 3: // JR d
|
|
jrConditional(true);
|
|
cycles += 3;
|
|
break;
|
|
default: // JR cc,d
|
|
jrConditionalFlag(y - 4);
|
|
cycles += 2;
|
|
break;
|
|
}
|
|
break;
|
|
case 1: // 16-bit load immediate/add
|
|
switch (q) {
|
|
case 0: // LD rp,nn
|
|
RP(p) = fetchWord();
|
|
cycles += 3;
|
|
break;
|
|
case 1: // ADD HL,rp
|
|
RP(HL_IDX) = add(RP(p));
|
|
cycles += 2;
|
|
break;
|
|
}
|
|
break;
|
|
case 2: // Indirect loading
|
|
switch (q) {
|
|
case 0:
|
|
switch (p) {
|
|
case 0: // LD (BC),A
|
|
m_memory.set(BC().word, A());
|
|
cycles += 2;
|
|
break;
|
|
case 1: // LD (DE),A
|
|
m_memory.set(DE().word, A());
|
|
cycles += 2;
|
|
break;
|
|
case 2: // GB: LDI (HL),A
|
|
m_memory.set(HL().word++, A());
|
|
cycles += 2;
|
|
break;
|
|
case 3: // GB: LDD (HL),A
|
|
m_memory.set(HL().word--, A());
|
|
cycles += 2;
|
|
break;
|
|
}
|
|
break;
|
|
case 1:
|
|
switch (p) {
|
|
case 0: // LD A,(BC)
|
|
A() = m_memory.get(BC().word);
|
|
cycles += 2;
|
|
break;
|
|
case 1: // LD A,(DE)
|
|
A() = m_memory.get(DE().word);
|
|
cycles += 2;
|
|
break;
|
|
case 2: // GB: LDI A,(HL)
|
|
A() = m_memory.get(HL().word++);
|
|
cycles += 2;
|
|
break;
|
|
case 3: // GB: LDD A,(HL)
|
|
A() = m_memory.get(HL().word--);
|
|
cycles += 2;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
case 3: // 16-bit INC/DEC
|
|
switch (q) {
|
|
case 0: // INC rp
|
|
++RP(p);
|
|
break;
|
|
case 1: // DEC rp
|
|
--RP(p);
|
|
break;
|
|
}
|
|
cycles += 2;
|
|
break;
|
|
case 4: // 8-bit INC
|
|
postIncrement(++R(y)); // INC r
|
|
cycles++;
|
|
if (y == 6)
|
|
cycles += 2;
|
|
break;
|
|
case 5: // 8-bit DEC
|
|
postDecrement(--R(y)); // DEC r
|
|
cycles++;
|
|
if (y == 6)
|
|
cycles += 2;
|
|
break;
|
|
case 6: // 8-bit load immediate
|
|
R(y) = fetchByte();
|
|
cycles += 2;
|
|
break;
|
|
case 7: // Assorted operations on accumulator/flags
|
|
switch (y) {
|
|
case 0:
|
|
rlca();
|
|
break;
|
|
case 1:
|
|
rrca();
|
|
break;
|
|
case 2:
|
|
rla();
|
|
break;
|
|
case 3:
|
|
rra();
|
|
break;
|
|
case 4:
|
|
daa();
|
|
break;
|
|
case 5:
|
|
cpl();
|
|
break;
|
|
case 6:
|
|
scf();
|
|
break;
|
|
case 7:
|
|
ccf();
|
|
break;
|
|
}
|
|
cycles++;
|
|
break;
|
|
}
|
|
break;
|
|
case 1: // 8-bit loading
|
|
if (z == 6 && y == 6) { // Exception (replaces LD (HL), (HL))
|
|
halt();
|
|
} else {
|
|
R(y) = R(z);
|
|
if ((y == 6) || (z == 6)) // M operations
|
|
cycles++;
|
|
}
|
|
cycles++;
|
|
break;
|
|
case 2: // Operate on accumulator and register/memory location
|
|
switch (y) {
|
|
case 0: // ADD A,r
|
|
add(A(), R(z));
|
|
break;
|
|
case 1: // ADC A,r
|
|
adc(A(), R(z));
|
|
break;
|
|
case 2: // SUB r
|
|
sub(A(), R(z));
|
|
break;
|
|
case 3: // SBC A,r
|
|
sbc(A(), R(z));
|
|
break;
|
|
case 4: // AND r
|
|
anda(R(z));
|
|
break;
|
|
case 5: // XOR r
|
|
xora(R(z));
|
|
break;
|
|
case 6: // OR r
|
|
ora(R(z));
|
|
break;
|
|
case 7: // CP r
|
|
compare(R(z));
|
|
break;
|
|
}
|
|
cycles++;
|
|
if (z == 6)
|
|
cycles++;
|
|
break;
|
|
case 3:
|
|
switch (z) {
|
|
case 0: // Conditional return
|
|
returnConditionalFlag(y);
|
|
cycles += 2;
|
|
break;
|
|
case 1: // POP & various ops
|
|
switch (q) {
|
|
case 0: // POP rp2[p]
|
|
RP2(p) = popWord();
|
|
cycles += 3;
|
|
break;
|
|
case 1:
|
|
switch (p) {
|
|
case 0: // RET
|
|
ret();
|
|
cycles += 4;
|
|
break;
|
|
case 1: // GB: RETI
|
|
reti();
|
|
cycles += 4;
|
|
break;
|
|
case 2: // JP HL
|
|
pc = HL().word;
|
|
cycles += 1;
|
|
break;
|
|
case 3: // LD SP,HL
|
|
sp = HL().word;
|
|
cycles += 2;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case 2: // Conditional jump
|
|
jumpConditionalFlag(y);
|
|
cycles += 3;
|
|
break;
|
|
case 3: // Assorted operations
|
|
switch (y) {
|
|
case 0: // JP nn
|
|
pc = fetchWord();
|
|
cycles += 4;
|
|
break;
|
|
case 1: // CB prefix
|
|
m_prefixCB = true;
|
|
fetchExecute();
|
|
break;
|
|
case 6: // DI
|
|
di();
|
|
cycles++;
|
|
break;
|
|
case 7: // EI
|
|
ei();
|
|
cycles++;
|
|
break;
|
|
}
|
|
break;
|
|
case 4: // Conditional call: CALL cc[y], nn
|
|
callConditionalFlag(getWord(pc), y);
|
|
cycles += 3;
|
|
break;
|
|
case 5: // PUSH & various ops
|
|
switch (q) {
|
|
case 0: // PUSH rp2[p]
|
|
pushWord(RP2(p));
|
|
cycles += 4;
|
|
break;
|
|
case 1:
|
|
switch (p) {
|
|
case 0: // CALL nn
|
|
callConditional(getWord(pc), true);
|
|
cycles += 3;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
switch (y) {
|
|
case 0: // ADD A,n
|
|
add(A(), fetchByte());
|
|
break;
|
|
case 1: // ADC A,n
|
|
adc(A(), fetchByte());
|
|
break;
|
|
case 2: // SUB n
|
|
sub(A(), fetchByte());
|
|
break;
|
|
case 3: // SBC A,n
|
|
sbc(A(), fetchByte());
|
|
break;
|
|
case 4: // AND n
|
|
anda(fetchByte());
|
|
break;
|
|
case 5: // XOR n
|
|
xora(fetchByte());
|
|
break;
|
|
case 6: // OR n
|
|
ora(fetchByte());
|
|
break;
|
|
case 7: // CP n
|
|
compare(fetchByte());
|
|
break;
|
|
}
|
|
cycles += 2;
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
restart(y << 3);
|
|
cycles += 4;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
} |