725 lines
14 KiB
C++
725 lines
14 KiB
C++
#include "stdafx.h"
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#include "Disassembler.h"
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#include <sstream>
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#include <iomanip>
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#include <bitset>
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#include "Memory.h"
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#include "Z80.h"
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Disassembler::Disassembler() {
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// Disable exceptions where too many format arguments are available
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m_formatter.exceptions(boost::io::all_error_bits ^ boost::io::too_many_args_bit);
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}
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std::string Disassembler::state(Z80& cpu) {
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auto pc = cpu.getProgramCounter();
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auto sp = cpu.getStackPointer();
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auto a = cpu.A();
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auto f = cpu.F();
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auto b = cpu.B();
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auto c = cpu.C();
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auto d = cpu.D();
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auto e = cpu.E();
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auto h = cpu.H();
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auto l = cpu.L();
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auto i = cpu.IV();
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auto r = cpu.REFRESH();
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auto im = cpu.IM();
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std::ostringstream output;
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output
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<< "PC=" << hex(pc.word)
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<< " "
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<< "SP=" << hex(sp.word)
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<< " " << "A=" << hex(a) << " " << "F=" << flags(f)
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<< " " << "B=" << hex(b) << " " << "C=" << hex(c)
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<< " " << "D=" << hex(d) << " " << "E=" << hex(e)
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<< " " << "H=" << hex(h) << " " << "L=" << hex(l)
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<< " " << "I=" << hex(i) << " " << "R=" << hex(r)
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<< " " << "IM=" << im;
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return output.str();
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}
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std::string Disassembler::RP(int rp) const {
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switch (rp) {
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case 0:
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return "BC";
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case 1:
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return "DE";
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case 2:
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if (m_prefixDD)
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return "IX";
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if (m_prefixFD)
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return "IY";
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return "HL";
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case 3:
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return "SP";
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}
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throw std::logic_error("Unhandled register pair");
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}
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std::string Disassembler::RP2(int rp) const {
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switch (rp) {
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case 0:
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return "BC";
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case 1:
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return "DE";
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case 2:
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if (m_prefixDD)
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return "IX";
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if (m_prefixFD)
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return "IY";
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return "HL";
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case 3:
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return "AF";
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}
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throw std::logic_error("Unhandled register pair");
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}
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std::string Disassembler::R(int r) const {
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switch (r) {
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case 0:
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return "B";
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case 1:
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return "C";
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case 2:
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return "D";
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case 3:
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return "E";
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case 4:
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if (m_prefixDD)
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return "IXH";
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if (m_prefixFD)
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return "IYH";
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return "H";
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case 5:
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if (m_prefixDD)
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return "IXL";
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if (m_prefixFD)
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return "IYL";
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return "L";
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case 6:
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if (m_prefixDD || m_prefixFD) {
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if (m_prefixDD)
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return "IX+%4%";
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if (m_prefixFD)
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return "IY+%4%";
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}
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else {
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return "(HL)";
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}
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case 7:
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return "A";
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}
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throw std::logic_error("Unhandled register");
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}
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std::string Disassembler::cc(int flag) {
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switch (flag) {
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case 0:
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return "NZ";
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case 1:
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return "Z";
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case 2:
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return "NC";
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case 3:
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return "C";
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case 4:
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return "PO";
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case 5:
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return "PE";
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case 6:
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return "P";
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case 7:
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return "M";
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}
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throw std::logic_error("Unhandled condition");
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}
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std::string Disassembler::alu(int which) {
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switch (which) {
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case 0: // ADD A,n
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return "ADD";
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case 1: // ADC
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return "ADC";
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case 2: // SUB n
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return "SUB";
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case 3: // SBC A,n
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return "SBC";
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case 4: // AND n
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return "AND";
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case 5: // XOR n
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return "XOR";
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case 6: // OR n
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return "OR";
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case 7: // CP n
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return "CP";
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}
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throw std::logic_error("Unhandled alu operation");
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}
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std::string Disassembler::disassemble(const Z80& cpu) {
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m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
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std::ostringstream output;
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disassemble(output, cpu, cpu.getProgramCounter().word);
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return output.str();
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}
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void Disassembler::disassemble(std::ostringstream& output, const Z80& cpu, uint16_t pc) {
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const auto& memory = cpu.getMemory();
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auto opcode = memory.peek(pc);
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// hex opcode
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output << hex(opcode);
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auto x = (opcode & 0b11000000) >> 6;
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auto y = (opcode & 0b111000) >> 3;
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auto z = (opcode & 0b111);
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auto p = (y & 0b110) >> 1;
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auto q = (y & 1);
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auto immediate = memory.peek(pc + 1);
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auto absolute = memory.peekWord(pc + 1);
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auto displacement = (int8_t)immediate;
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auto relative = pc + displacement + 2;
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auto indexedImmediate = memory.peek(pc + 1);
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auto dumpCount = 0;
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std::string specification = "";
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if (m_prefixCB)
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disassembleCB(
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output, cpu, pc,
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specification, dumpCount,
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x, y, z, p, q);
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else if (m_prefixED)
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disassembleED(
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output, cpu, pc,
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specification, dumpCount,
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x, y, z, p, q);
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else
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disassembleOther(
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output, cpu, pc,
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specification, dumpCount,
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x, y, z, p, q);
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for (int i = 0; i < dumpCount; ++i)
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output << hex(memory.peek(pc + i + 1));
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auto outputFormatSpecification = !m_prefixDD;
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if (m_prefixDD) {
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if (opcode != 0xdd) {
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outputFormatSpecification = true;
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}
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}
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if (outputFormatSpecification) {
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output << '\t';
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m_formatter.parse(specification);
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output << m_formatter % (int)immediate % (int)absolute % relative % (int)displacement % indexedImmediate;
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}
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}
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void Disassembler::disassembleCB(
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std::ostringstream& output,
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const Z80& cpu,
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uint16_t pc,
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std::string& specification,
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int& dumpCount,
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int x, int y, int z,
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int p, int q) {
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switch (x) {
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case 0: // rot[y] r[z]
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switch (y) {
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case 0:
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specification = "RLC " + R(z);
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break;
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case 1:
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specification = "RRC " + R(z);
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break;
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case 2:
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specification = "RL " + R(z);
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break;
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case 3:
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specification = "RR " + R(z);
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break;
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case 4:
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specification = "SLA " + R(z);
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break;
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case 5:
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specification = "SRA " + R(z);
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break;
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case 6:
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specification = "SWAP " + R(z);
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break;
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case 7:
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specification = "SRL " + R(z);
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break;
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}
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break;
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case 1: // BIT y, r[z]
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specification = "BIT " + decimal(y) + "," + R(z);
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break;
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case 2: // RES y, r[z]
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specification = "RES " + decimal(y) + "," + R(z);
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break;
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case 3: // SET y, r[z]
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specification = "SET " + decimal(y) + "," + R(z);
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break;
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}
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}
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void Disassembler::disassembleED(
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std::ostringstream& output,
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const Z80& cpu,
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uint16_t pc,
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std::string& specification,
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int& dumpCount,
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int x, int y, int z,
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int p, int q) {
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switch (x) {
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case 0:
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case 3:
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specification = "NONI NOP";
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break;
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case 1:
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switch (z) {
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case 2:
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switch (q) {
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case 0: // SBC HL,rp
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specification = "SBC HL," + RP(p);
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break;
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case 1: // ADC HL,rp
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specification = "ADC HL," + RP(p);
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break;
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}
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case 3:
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switch (q) {
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case 0: // LD (nn),rp
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specification = "LD (%2$04XH)," + RP(p);
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break;
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case 1: // LD rp,(nn)
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specification = "LD " + RP(p) + ",(%2$04XH)";
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break;
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}
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dumpCount += 2;
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break;
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case 7:
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switch (y) {
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case 0:
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specification = "LD I,A";
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break;
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case 1:
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specification = "LD R,A";
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break;
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case 2:
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specification = "LD A,I";
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break;
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case 3:
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specification = "LD A,R";
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break;
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case 4:
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specification = "RRD";
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break;
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case 5:
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specification = "RLD";
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break;
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case 6:
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case 7:
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specification = "NOP";
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break;
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}
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break;
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}
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break;
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case 2:
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switch (z) {
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case 0: // LD
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switch (y) {
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case 4: // LDI
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specification = "LDI";
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break;
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case 5: // LDD
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specification = "LDD";
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break;
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case 6: // LDIR
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specification = "LDIR";
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break;
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case 7: // LDDR
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specification = "LDDR";
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break;
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}
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break;
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case 1: // CP
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switch (y) {
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case 4: // CPI
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specification = "CPI";
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break;
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case 5: // CPD
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specification = "CPD";
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break;
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case 6: // CPIR
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specification = "CPIR";
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break;
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case 7: // CPDR
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specification = "CPDR";
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break;
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}
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break;
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case 2: // IN
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switch (y) {
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case 4: // INI
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specification = "INI";
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break;
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case 5: // IND
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specification = "IND";
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break;
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case 6: // INIR
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specification = "INIR";
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break;
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case 7: // INDR
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specification = "INDR";
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break;
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}
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break;
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case 3: // OUT
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switch (y) {
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case 4: // OUTI
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specification = "OUTI";
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break;
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case 5: // OUTD
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specification = "OUTD";
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break;
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case 6: // OTIR
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specification = "OTIR";
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break;
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case 7: // OTDR
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specification = "OTDR";
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break;
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}
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break;
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}
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break;
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}
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}
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void Disassembler::disassembleOther(
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std::ostringstream& output,
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const Z80& cpu,
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uint16_t pc,
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std::string& specification,
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int& dumpCount,
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int x, int y, int z,
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int p, int q) {
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switch (x) {
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case 0:
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switch (z) {
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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specification = "NOP";
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break;
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case 1: // EX AF AF'
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specification = "EX AF AF'";
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break;
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case 2: // DJNZ d
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specification = "DJNZ %3$04XH";
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dumpCount += 2;
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break;
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case 3: // JR d
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specification = "JR %3$04XH";
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dumpCount++;
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break;
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default: // JR cc,d
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specification = "JR " + cc(y - 4) + ",%3$04XH";
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dumpCount++;
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q) {
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case 0: // LD rp,nn
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specification = "LD " + RP(p) + ",%2$04XH";
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dumpCount += 2;
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break;
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case 1: // ADD HL,rp
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specification = "ADD HL," + RP(p);
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q) {
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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specification = "LD (BC),A";
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break;
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case 1: // LD (DE),A
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specification = "LD (DE),A";
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break;
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case 2: // LD (nn),HL
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specification = "LD (%2$04XH),HL";
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dumpCount += 2;
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break;
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case 3: // LD (nn),A
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specification = "LD (%2$04XH),A";
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dumpCount += 2;
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break;
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}
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break;
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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specification = "LD A,(BC)";
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break;
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case 1: // LD A,(DE)
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specification = "LD A,(DE)";
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break;
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case 2: // LD HL,(nn)
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specification = "LD HL,(%2$04XH)";
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dumpCount += 2;
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break;
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case 3: // LD A,(nn)
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specification = "LD A,(%2$04XH)";
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dumpCount += 2;
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break;
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}
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break;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q) {
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case 0: // INC rp
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specification = "INC " + RP(p);
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break;
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case 1: // DEC rp
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specification = "DEC " + RP(p);
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break;
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}
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break;
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case 4: // 8-bit INC
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specification = "INC " + R(y);
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break;
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case 5: // 8-bit DEC
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specification = "DEC " + R(y);
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break;
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case 6: // 8-bit load immediate
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specification = "LD " + R(y);
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if (y == 6 && (m_prefixDD || m_prefixFD)) {
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specification += ",%5$02XH";
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dumpCount++;
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} else {
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specification += ",%1$02XH";
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}
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dumpCount++;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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case 0:
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specification = "RLCA";
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break;
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case 1:
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specification = "RRCA";
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break;
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case 2:
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specification = "RLA";
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break;
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case 3:
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specification = "RRA";
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break;
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case 4:
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specification = "DAA";
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break;
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case 5:
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specification = "CPL";
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break;
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case 6:
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specification = "SCF";
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break;
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case 7:
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specification = "CCF";
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break;
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}
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break;
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}
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break;
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case 1: // 8-bit loading
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if (z == 6 && y == 6) { // Exception (replaces LD (HL), (HL))
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specification = "HALT";
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} else {
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specification = "LD " + R(y) + "," + R(z);
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}
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break;
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case 2: // Operate on accumulator and register/memory location
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specification = alu(y) + " A," + R(z);
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break;
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case 3:
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switch (z) {
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case 0: // Conditional return
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specification = "RET " + cc(y);
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break;
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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specification = "POP " + RP2(p);
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break;
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case 1:
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switch (p) {
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case 0: // RET
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specification = "RET";
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break;
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case 1: // EXX
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specification = "EXX";
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break;
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case 2: // JP (HL)
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specification = "JP (HL)";
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break;
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case 3: // LD SP,HL
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specification = "LD SP,Hl";
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break;
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}
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}
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break;
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|
case 2: // Conditional jump
|
|
specification = "JP " + cc(y) + ",%2$04XH";
|
|
dumpCount += 2;
|
|
break;
|
|
case 3: // Assorted operations
|
|
switch (y) {
|
|
case 0: // JP nn
|
|
specification = "JP %2$04XH";
|
|
dumpCount += 2;
|
|
break;
|
|
case 1: // CB prefix
|
|
m_prefixCB = true;
|
|
disassemble(output, cpu, pc + 1);
|
|
break;
|
|
case 2: // OUT (n),A
|
|
specification = "OUT (%1$02XH),A";
|
|
dumpCount++;
|
|
break;
|
|
case 3: // IN A,(n)
|
|
specification = "IN A,(%1$02XH)";
|
|
dumpCount++;
|
|
break;
|
|
case 4: // EX (SP),HL
|
|
specification = "EX (SP),HL";
|
|
break;
|
|
case 5: // EX DE,HL
|
|
specification = "EX DE,HL";
|
|
break;
|
|
case 6: // DI
|
|
specification = "DI";
|
|
break;
|
|
case 7: // EI
|
|
specification = "EI";
|
|
break;
|
|
}
|
|
break;
|
|
case 4: // Conditional call: CALL cc[y], nn
|
|
specification = "CALL " + cc(y) + ",%2$04XH";
|
|
dumpCount += 2;
|
|
break;
|
|
case 5: // PUSH & various ops
|
|
switch (q) {
|
|
case 0: // PUSH rp2[p]
|
|
specification = "PUSH " + RP2(p);
|
|
break;
|
|
case 1:
|
|
switch (p) {
|
|
case 0: // CALL nn
|
|
specification = "CALL %2$04XH";
|
|
dumpCount += 2;
|
|
break;
|
|
case 1: // DD prefix
|
|
m_prefixDD = true;
|
|
disassemble(output, cpu, pc + 1);
|
|
break;
|
|
case 2: // ED prefix
|
|
m_prefixED = true;
|
|
disassemble(output, cpu, pc + 1);
|
|
break;
|
|
case 3: // FD prefix
|
|
m_prefixFD = true;
|
|
disassemble(output, cpu, pc + 1);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
specification = alu(y) + " A,%1$02XH";
|
|
dumpCount++;
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
specification = "RST " + hex((uint8_t)(y * 8));
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
std::string Disassembler::flag(uint8_t value, int flag, const std::string& represents) {
|
|
std::ostringstream output;
|
|
output << (value & flag ? represents : "-");
|
|
return output.str();
|
|
}
|
|
|
|
std::string Disassembler::flags(uint8_t value) {
|
|
std::ostringstream output;
|
|
output
|
|
<< flag(value, Z80::SF, "S")
|
|
<< flag(value, Z80::ZF, "Z")
|
|
<< flag(value, Z80::YF, "Y")
|
|
<< flag(value, Z80::HC, "H")
|
|
<< flag(value, Z80::XF, "X")
|
|
<< flag(value, Z80::PF, "P")
|
|
<< flag(value, Z80::NF, "N")
|
|
<< flag(value, Z80::CF, "C");
|
|
return output.str();
|
|
}
|
|
|
|
std::string Disassembler::hex(uint8_t value) {
|
|
std::ostringstream output;
|
|
output << std::hex << std::setw(2) << std::setfill('0') << (int)value;
|
|
return output.str();
|
|
}
|
|
|
|
std::string Disassembler::hex(uint16_t value) {
|
|
std::ostringstream output;
|
|
output << std::hex << std::setw(4) << std::setfill('0') << (int)value;
|
|
return output.str();
|
|
}
|
|
|
|
std::string Disassembler::binary(uint8_t value) {
|
|
std::ostringstream output;
|
|
output << std::bitset<8>(value);
|
|
return output.str();
|
|
}
|
|
|
|
std::string Disassembler::decimal(uint8_t value) {
|
|
std::ostringstream output;
|
|
output << (int)value;
|
|
return output.str();
|
|
}
|
|
|
|
std::string Disassembler::invalid(uint8_t value) {
|
|
std::ostringstream output;
|
|
output << "Invalid instruction: " << hex(value) << "(" << binary(value) << ")";
|
|
return output.str();
|
|
} |