mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2024-06-08 22:29:40 +00:00
306 lines
13 KiB
C++
306 lines
13 KiB
C++
#pragma once
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#include <cstdint>
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#include <ClockedChip.h>
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#include <Signal.h>
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namespace EightBit {
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class mc6850 final : public ClockedChip {
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public:
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// Receive data, (I) Active high
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DECLARE_PIN_INPUT(RXDATA)
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// Transmit data, (O) Active high
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DECLARE_PIN_OUTPUT(TXDATA)
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// Request to send, (O) Active low
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DECLARE_PIN_OUTPUT(RTS)
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// Clear to send, (I) Active low
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DECLARE_PIN_INPUT(CTS)
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// Data carrier detect, (I) Active low
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DECLARE_PIN_INPUT(DCD)
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// Transmit clock, (I) Active high
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DECLARE_PIN_INPUT(RXCLK)
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// Receive clock, (I) Active high
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DECLARE_PIN_INPUT(TXCLK)
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// Chip select, bit 0, (I) Active high
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DECLARE_PIN_INPUT(CS0)
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// Chip select, bit 1, (I) Active high
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DECLARE_PIN_INPUT(CS1)
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// Chip select, bit 2, (I) Active low
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DECLARE_PIN_INPUT(CS2)
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// Register select, (I) Active high
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DECLARE_PIN_INPUT(RS)
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// Read/Write, (I) Read high, write low
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DECLARE_PIN_INPUT(RW)
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// ACIA Enable, (I) Active high
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DECLARE_PIN_INPUT(E)
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// Interrupt request, (O) Active low
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DECLARE_PIN_OUTPUT(IRQ)
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public:
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mc6850();
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// +--------+----------------------------------------------------------------------------------+
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// | | Buffer address |
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// | +------------------+------------------+--------------------+-----------------------+
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// | | _ | _ | _ | _ |
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// | Data | RS * R/W | RS * R/W | RS * R/W | RS * R/W |
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// | Bus | (high)(low) | (high)(high) | (low)(low) | (low)(low) |
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// | Line | Transmit | Receive | | |
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// | Number | Data | Data | Control | Status |
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// | | Register | Register | Register | register |
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// | +------------------+------------------+--------------------+-----------------------+
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// | | (Write only) | (Read only) | (Write only) | (Read only) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 0 | Data bit 0* | Data bit 0 | Counter divide | Receive data register |
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// | | | | select 1 (CR0) | full (RDRF) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 1 | Data bit 1 | Data bit 1 | Counter divide | Transmit data register|
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// | | | | select 2 (CR1) | empty (TDRE) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 2 | Data bit 2 | Data bit 2 | Word select 1 | Data carrier detect |
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// | | | | (CR2) | (DCD active) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 3 | Data bit 3 | Data bit 3 | Word select 1 | Clear to send |
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// | | | | (CR3) | (CTS active) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 4 | Data bit 4 | Data bit 4 | Word select 1 | Framing error |
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// | | | | (CR4) | (FE) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 5 | Data bit 5 | Data bit 5 | Transmit control 1 | Receiver overrun |
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// | | | | (CR5) | (OVRN) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 6 | Data bit 6 | Data bit 6 | Transmit control 2 | Parity error (PE) |
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// | | | | (CR6) | |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 7 | Data bit 7*** | Data bit 7** | Receive interrupt | Interrupt request |
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// | | | | enable (CR7) | (IRQ active) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// * Leading bit = LSB = Bit 0
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// ** Data bit will be zero in 7-bit plus parity modes
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// *** Data bit is "don't care" in 7-bit plus parity modes
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enum ControlRegisters {
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CR0 = 0b1, // Counter divide
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CR1 = 0b10, // "
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CR2 = 0b100, // Word select
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CR3 = 0b1000, // "
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CR4 = 0b10000, // "
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CR5 = 0b100000, // Transmit control
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CR6 = 0b1000000, // "
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CR7 = 0b10000000 // Receive control
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};
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// CR0 and CR1
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enum CounterDivideSelect {
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One = 0b00,
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Sixteen = 0b01,
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SixtyFour = 0b10,
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MasterReset = 0b11
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};
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// CR2, CR3 and CR4
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enum WordSelect {
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SevenEvenTwo = 0b000,
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SevenOddTwo = 0b001,
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SevenEvenOne = 0b010,
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SevenOddOne = 0b011,
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EightTwo = 0b100,
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EightOne = 0b101,
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EightEvenOne = 0b110,
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EightOddOne = 0b111,
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};
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// CR5 and CR6
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enum TransmitterControl {
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ReadyLowInterruptDisabled = 0b00,
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ReadyLowInterruptEnabled = 0b01,
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ReadyHighInterruptDisabled = 0b10,
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ReadyLowInterruptDisabledTransmitBreak = 0b11,
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};
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// CR7
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enum ReceiveControl {
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ReceiveInterruptDisable = 0b0,
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ReceiveInterruptEnable = 0b1, // Triggers on: RDR full, overrun, DCD low -> high
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};
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// STATUS REGISTER Information on the status of the ACIA is
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// available to the MPU by reading the ACIA Status Register.
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// This read-only register is selected when RS is low and R/W is high.
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// Information stored in this register indicates the status of the
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// Transmit Data Register, the Receive Data Register and error logic,
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// and the peripheral/modem status inputs of the ACIA
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enum StatusRegisters {
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// Receive Data Register Full (RDRF), Bit 0 - Receive Data
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// Register Full indicates that received data has been
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// transferred to the Receive Data Register. RDRF is cleared
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// after an MPU read of the Receive Data Register or by a
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// master reset. The cleared or empty state indicates that the
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// contents of the Receive Data Register are not current.
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// Data Carrier Detect being high also causes RDRF to indicate
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// empty.
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STATUS_RDRF = 0b1,
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// Transmit Data Register Empty (TDRE), Bit 1 - The Transmit
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// Data Register Empty bit being set high indicates that the
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// Transmit Data Register contents have been transferred and
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// that new data may be entered. The low state indicates that
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// the register is full and that transmission of a new
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// character has not begun since the last write data command.
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STATUS_TDRE = 0b10,
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// ___
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// Data Carrier Detect (DCD), Bit 2 - The Data Carrier Detect
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// bit will be high when the DCD (low) input from a modem has gone
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// high to indicate that a carrier is not present. This bit
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// going high causes an Interrupt Request to be generated when
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// the Receive Interrupt Enable is set. It remains high after
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// the DCD (low) input is returned low until cleared by first reading
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// the Status Register and then the Data Register or until a
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// master reset occurs. If the DCD (low) input remains high after
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// read status and read data or master reset has occurred, the
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// interrupt is cleared, the DCD (low) status bit remains high and
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// will follow the DCD (low) input.
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STATUS_DCD = 0b100,
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// ___
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// Clear-to-Send (CTS), Bit 3 - The Clear-to-Send bit indicates
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// the state of the Clear-to-Send input from a modem. A low CTS (low)
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// indicates that there is a Clear-to-Send from the modem. In
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// the high state, the Transmit Data Register Empty bit is
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// inhibited and the Clear-to-Send status bit will be high.
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// Master reset does not affect the Clear-to-Send status bit.
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STATUS_CTS = 0b1000,
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// Framing Error (FE), Bit 4 - Framing error indicates that the
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// received character is improperly framed by a start and a
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// stop bit and is detected by the absence of the first stop
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// bit. This error indicates a synchronization error, faulty
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// transmission, or a break condition. The framing error flag
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// is set or reset during the receive data transfer time.
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// Therefore, this error indicator is present throughout the
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// time that the associated character is available.
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STATUS_FE = 0b10000,
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// Receiver Overrun (OVRN), Bit 5- Overrun is an error flag
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// that indicates that one or more characters in the data
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// stream were lost. That is, a character or a number of
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// characters were received but not read from the Receive
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// Data Register (RDR) prior to subsequent characters being
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// received. The overrun condition begins at the midpoint of
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// the last bit of the second character received in succession
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// without a read of the RDR having occurred. The Overrun does
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// not occur in the Status Register until the valid character
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// prior to Overrun has been read. The RDRF bit remains set
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// until the Overrun is reset. Character synchronization is
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// maintained during the Overrun condition. The Overrun
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// indication is reset after the reading of data from the
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// Receive Data Register or by a Master Reset.
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STATUS_OVRN = 0b100000,
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// Parity Error (PE), Bit 6 - The parity error flag indicates
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// that the number of highs {ones) in the character does not
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// agree with the preselected odd or even parity. Odd parity
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// is defined to be when the total number of ones is odd. The
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// parity error indication will be present as long as the data
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// character is in the RDR. If no parity is selected, then both
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// the transmitter parity generator output and the receiver
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// parity check results are inhibited
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STATUS_PE = 0b1000000,
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// ___
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// Interrupt Request (IRQ), Bit 7- The IRQ (low) bit indicates the
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// state of the IRQ (low) output. Any interrupt condition with its
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// applicable enable will be indicated in this status bit.
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// Anytime the IRQ (low) output is low the IRQ bit will be high to
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// indicate the interrupt or service request status. IRQ (low) is
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// cleared by a read operation to the Receive Data Register or
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// a write operation to the Transmit Data Register.
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STATUS_IRQ = 0b10000000,
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};
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// Data, (I/O)
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auto& DATA() { return m_data; }
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// Expose these internal registers, so we can update internal state
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// Transmit data register;
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auto& TDR() { return m_TDR; }
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// Receive data register;
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auto& RDR() { return m_RDR; }
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bool activated() { return powered() && raised(E()) && selected(); }
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bool selected() { return raised(CS0()) && raised(CS1()) && lowered(CS2()); }
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void markTransmitComplete();
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void markReceiveStarting();
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std::string dumpStatus();
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Signal<EventArgs> Accessing;
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Signal<EventArgs> Accessed;
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Signal<EventArgs> Transmitting;
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Signal<EventArgs> Transmitted;
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Signal<EventArgs> Receiving;
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Signal<EventArgs> Received;
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private:
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void step();
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uint8_t status();
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void reset();
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void startTransmit();
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void completeReceive();
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bool transmitInterruptEnabled() const { return m_transmitControl == ReadyLowInterruptEnabled; }
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bool receiveInterruptEnabled() const { return m_receiveControl == ReceiveInterruptEnable; }
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bool transmitReadyHigh() const { return m_transmitControl == ReadyHighInterruptDisabled; }
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bool transmitReadyLow() const { return !transmitReadyHigh(); }
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PinLevel m_oldDCD = PinLevel::Low; // So we can detect low -> high transition
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uint8_t m_data = 0;
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bool m_statusRead = false;
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// Control registers
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CounterDivideSelect m_counterDivide = CounterDivideSelect::One;
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WordSelect m_wordSelect = WordSelect::SevenEvenTwo;
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TransmitterControl m_transmitControl = TransmitterControl::ReadyLowInterruptDisabled;
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ReceiveControl m_receiveControl = ReceiveControl::ReceiveInterruptDisable;
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// Status registers
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bool m_statusRDRF = false;
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bool m_statusTDRE = true;
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bool m_statusOVRN = false;
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// Data registers
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uint8_t m_TDR = 0;
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uint8_t m_RDR = 0;
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enum StartupCondition { ColdStart, WarmStart, Unknown };
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StartupCondition m_startup = WarmStart;
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};
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}
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