EightBit/MC6809/unittest/mc6809_tests.cpp

#include "pch.h"
#include "Board.h"

// Using examples from 6809 Assembly Language Programming, by Lance A. Leventhal
// Just test the basics...

TEST_CASE("Add Accumulator B to Index Register X Unsigned", "[ABX]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Inherent") {
		board.poke(0, 0x3a);
		cpu.B() = 0x84;
		cpu.X() = 0x1097;
		cpu.step();
		REQUIRE(cpu.X() == 0x111b);
		REQUIRE(cpu.cycles() == 3);
    }
}

TEST_CASE("Add Memory Plus Carry to Accumulator A", "[ADC][ADCA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Immediate (byte)") {
		board.poke(0, 0x89);
		board.poke(1, 0x7c);
		EightBit::Chip::setFlag(cpu.CC(), EightBit::mc6809::CF);
		cpu.A() = 0x3a;
		cpu.step();
		REQUIRE(cpu.A() == 0xb7);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::HF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::VF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::CF) == 0);
		REQUIRE(cpu.cycles() == 2);
    }
}

TEST_CASE("Add Memory to Accumulator A", "[ADD][ADDA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Immediate (byte)") {
		board.poke(0, 0x8b);
		board.poke(1, 0x8b);
		cpu.A() = 0x24;
		cpu.step();
		REQUIRE(cpu.A() == 0xaf);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::HF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::VF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::CF) == 0);
		REQUIRE(cpu.cycles() == 2);
    }
}

TEST_CASE("Logical AND Accumulator", "[AND][ANDA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Immediate (byte)") {
		board.poke(0, 0x84);
		board.poke(1, 0x13);
		cpu.A() = 0xfc;
		cpu.step();
		REQUIRE(cpu.A() == 0x10);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::VF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) == 0);
		REQUIRE(cpu.cycles() == 2);
    }
}

TEST_CASE("Shift Accumulator or Memory Byte Left", "[ASL][ASLA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Inherent") {
		board.poke(0, 0x48);
		cpu.A() = 0x7a;
		cpu.step();
		REQUIRE(cpu.A() == 0xf4);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::VF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) != 0);
		REQUIRE(cpu.cycles() == 2);
    }
}

TEST_CASE("Shift Accumulator or Memory Byte Right", "[ASR][ASRA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Inherent") {
		board.poke(0, 0x47);
		cpu.A() = 0xcb;
		cpu.step();
		REQUIRE(cpu.A() == 0xe5);
		REQUIRE((cpu.CC() & EightBit::mc6809::CF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) != 0);
		REQUIRE(cpu.cycles() == 2);
    }
}

TEST_CASE("Bit Test", "[BIT][BITA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Immediate (byte)") {
		board.poke(0, 0x85);
		board.poke(1, 0xe0);
		cpu.A() = 0xa6;
		cpu.step();
		REQUIRE(cpu.A() == 0xa6);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) != 0);
		REQUIRE(cpu.cycles() == 2);
    }
}

TEST_CASE("Clear Accumulator or Memory", "[CLR][CLRA]") {

	Board board;
	board.initialise();
	auto& cpu = board.CPU();
	cpu.step();	// Step over the reset

    SECTION("Implied") {
		board.poke(0, 0x4f);
		cpu.A() = 0x43;
		cpu.step();
		REQUIRE(cpu.A() == 0x00);
		REQUIRE((cpu.CC() & EightBit::mc6809::CF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::ZF) != 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::NF) == 0);
		REQUIRE((cpu.CC() & EightBit::mc6809::VF) == 0);
		REQUIRE(cpu.cycles() == 2);
    }
}