669 lines
13 KiB
C++
669 lines
13 KiB
C++
#include "stdafx.h"
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#include "../inc/Intel8080.h"
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EightBit::Intel8080::Intel8080(Bus& bus)
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: IntelProcessor(bus) {
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RaisedPOWER.connect([this](EventArgs) {
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releaseMemory();
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releaseIO();
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releaseRead();
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releaseWrite();
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di();
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});
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}
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DEFINE_PIN_LEVEL_CHANGERS(DBIN, Intel8080);
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DEFINE_PIN_LEVEL_CHANGERS(WR, Intel8080);
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const EightBit::register16_t& EightBit::Intel8080::AF() const noexcept {
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auto* processor = const_cast<Intel8080*>(this);
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processor->af.low = (af.low | Bit1) & ~(Bit5 | Bit3);
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return af;
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}
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const EightBit::register16_t& EightBit::Intel8080::BC() const noexcept {
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return bc;
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}
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const EightBit::register16_t& EightBit::Intel8080::DE() const noexcept {
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return de;
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}
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const EightBit::register16_t& EightBit::Intel8080::HL() const noexcept {
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return hl;
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}
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void EightBit::Intel8080::memoryWrite() noexcept {
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requestMemory();
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IntelProcessor::memoryWrite();
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releaseMemory();
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}
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uint8_t EightBit::Intel8080::memoryRead() noexcept {
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requestMemory();
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const auto returned = IntelProcessor::memoryRead();
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releaseMemory();
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return returned;
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}
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void EightBit::Intel8080::busWrite() noexcept {
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requestWrite();
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IntelProcessor::busWrite();
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releaseWrite();
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}
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uint8_t EightBit::Intel8080::busRead() noexcept {
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requestRead();
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const auto returned = IntelProcessor::busRead();
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releaseRead();
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return returned;
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}
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void EightBit::Intel8080::handleRESET() noexcept {
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IntelProcessor::handleRESET();
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di();
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tick(3);
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}
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void EightBit::Intel8080::handleINT() noexcept {
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IntelProcessor::handleINT();
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raiseHALT();
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if (m_interruptEnable) {
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di();
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Processor::execute(BUS().DATA());
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}
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}
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void EightBit::Intel8080::di() {
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m_interruptEnable = false;
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}
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void EightBit::Intel8080::ei() {
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m_interruptEnable = true;
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}
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void EightBit::Intel8080::increment(uint8_t& operand) {
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F() = adjustSZP<Intel8080>(F(), ++operand);
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F() = clearBit(F(), AC, lowNibble(operand));
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}
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void EightBit::Intel8080::decrement(uint8_t& operand) {
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F() = adjustSZP<Intel8080>(F(), --operand);
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F() = setBit(F(), AC, lowNibble(operand) != Mask4);
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}
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int EightBit::Intel8080::jumpConditionalFlag(const int flag) {
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switch (flag) {
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case 0: // NZ
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return jumpConditional(!(F() & ZF));
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case 1: // Z
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return jumpConditional(F() & ZF);
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case 2: // NC
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return jumpConditional(!(F() & CF));
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case 3: // C
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return jumpConditional(F() & CF);
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case 4: // PO
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return jumpConditional(!(F() & PF));
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case 5: // PE
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return jumpConditional(F() & PF);
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case 6: // P
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return jumpConditional(!(F() & SF));
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case 7: // M
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return jumpConditional(F() & SF);
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default:
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UNREACHABLE;
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}
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}
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int EightBit::Intel8080::returnConditionalFlag(const int flag) {
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switch (flag) {
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case 0: // NZ
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return returnConditional(!(F() & ZF));
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case 1: // Z
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return returnConditional(F() & ZF);
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case 2: // NC
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return returnConditional(!(F() & CF));
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case 3: // C
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return returnConditional(F() & CF);
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case 4: // PO
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return returnConditional(!(F() & PF));
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case 5: // PE
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return returnConditional(F() & PF);
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case 6: // P
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return returnConditional(!(F() & SF));
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case 7: // M
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return returnConditional(F() & SF);
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default:
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UNREACHABLE;
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}
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}
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int EightBit::Intel8080::callConditionalFlag(const int flag) {
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switch (flag) {
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case 0: // NZ
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return callConditional(!(F() & ZF));
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case 1: // Z
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return callConditional(F() & ZF);
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case 2: // NC
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return callConditional(!(F() & CF));
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case 3: // C
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return callConditional(F() & CF);
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case 4: // PO
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return callConditional(!(F() & PF));
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case 5: // PE
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return callConditional(F() & PF);
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case 6: // P
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return callConditional(!(F() & SF));
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case 7: // M
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return callConditional(F() & SF);
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default:
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UNREACHABLE;
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}
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}
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void EightBit::Intel8080::add(const register16_t value) {
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const auto result = HL().word + value.word;
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HL() = result;
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F() = setBit(F(), CF, result & Bit16);
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}
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void EightBit::Intel8080::add(const uint8_t value, const int carry) {
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const register16_t result = A() + value + carry;
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adjustAuxiliaryCarryAdd(F(), A(), value, result.word);
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A() = result.low;
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F() = setBit(F(), CF, result.word & Bit8);
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F() = adjustSZP<Intel8080>(F(), A());
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}
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void EightBit::Intel8080::adc(const uint8_t value) {
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add(value, F() & CF);
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}
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void EightBit::Intel8080::subtract(uint8_t& operand, const uint8_t value, const int carry) {
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const register16_t result = operand - value - carry;
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adjustAuxiliaryCarrySub(F(), operand, value, result.word);
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operand = result.low;
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F() = setBit(F(), CF, result.word & Bit8);
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F() = adjustSZP<Intel8080>(F(), operand);
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}
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void EightBit::Intel8080::sbb(const uint8_t value) {
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subtract(A(), value, F() & CF);
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}
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void EightBit::Intel8080::andr(const uint8_t value) {
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F() = setBit(F(), AC, (A() | value) & Bit3);
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F() = clearBit(F(), CF);
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F() = adjustSZP<Intel8080>(F(), A() &= value);
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}
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void EightBit::Intel8080::xorr(const uint8_t value) {
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F() = clearBit(F(), AC | CF);
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F() = adjustSZP<Intel8080>(F(), A() ^= value);
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}
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void EightBit::Intel8080::orr(const uint8_t value) {
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F() = clearBit(F(), AC | CF);
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F() = adjustSZP<Intel8080>(F(), A() |= value);
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}
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void EightBit::Intel8080::compare(const uint8_t value) {
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auto original = A();
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subtract(original, value);
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}
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void EightBit::Intel8080::rlc() {
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const auto carry = A() & Bit7;
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A() = (A() << 1) | (carry >> 7);
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F() = setBit(F(), CF, carry);
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}
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void EightBit::Intel8080::rrc() {
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const auto carry = A() & Bit0;
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A() = (A() >> 1) | (carry << 7);
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F() = setBit(F(), CF, carry);
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}
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void EightBit::Intel8080::rl() {
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const auto carry = F() & CF;
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F() = setBit(F(), CF, A() & Bit7);
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A() = (A() << 1) | carry;
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}
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void EightBit::Intel8080::rr() {
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const auto carry = F() & CF;
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F() = setBit(F(), CF, A() & Bit0);
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A() = (A() >> 1) | (carry << 7);
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}
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void EightBit::Intel8080::daa() {
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const auto& before = A();
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auto carry = F() & CF;
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uint8_t addition = 0;
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if ((F() & AC) || lowNibble(before) > 9) {
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addition = 0x6;
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}
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if ((F() & CF) || highNibble(before) > 9 || (highNibble(before) >= 9 && lowNibble(before) > 9)) {
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addition |= 0x60;
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carry = true;
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}
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add(addition);
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F() = setBit(F(), CF, carry);
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}
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void EightBit::Intel8080::cma() {
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A() = ~A();
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}
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void EightBit::Intel8080::stc() {
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F() = setBit(F(), CF);
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}
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void EightBit::Intel8080::cmc() {
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F() = clearBit(F(), CF, F() & CF);
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}
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void EightBit::Intel8080::xhtl(register16_t& exchange) {
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MEMPTR().low = IntelProcessor::memoryRead(SP());
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++BUS().ADDRESS();
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MEMPTR().high = memoryRead();
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IntelProcessor::memoryWrite(exchange.high);
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exchange.high = MEMPTR().high;
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--BUS().ADDRESS();
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IntelProcessor::memoryWrite(exchange.low);
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exchange.low = MEMPTR().low;
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}
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void EightBit::Intel8080::portWrite(const uint8_t port) {
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BUS().ADDRESS() = { port, port };
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BUS().DATA() = A();
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portWrite();
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}
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void EightBit::Intel8080::portWrite() {
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requestIO();
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busWrite();
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releaseIO();;
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}
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uint8_t EightBit::Intel8080::portRead(const uint8_t port) {
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BUS().ADDRESS() = { port, port };
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return portRead();
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}
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uint8_t EightBit::Intel8080::portRead() {
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requestIO();
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const auto returned = busRead();
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releaseIO();;
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return returned;
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}
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int EightBit::Intel8080::step() noexcept {
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ExecutingInstruction.fire(*this);
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resetCycles();
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if (LIKELY(powered())) {
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if (UNLIKELY(lowered(RESET()))) {
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handleRESET();
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} else if (UNLIKELY(lowered(INT()))) {
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handleINT();
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} else if (UNLIKELY(lowered(HALT()))) {
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Processor::execute(0); // NOP
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} else {
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Processor::execute(fetchByte());
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}
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}
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ExecutedInstruction.fire(*this);
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ASSUME(cycles() > 0);
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return cycles();
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}
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void EightBit::Intel8080::execute() noexcept {
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const auto& decoded = getDecodedOpcode(opcode());
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const auto x = decoded.x;
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const auto y = decoded.y;
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const auto z = decoded.z;
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const auto p = decoded.p;
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const auto q = decoded.q;
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execute(x, y, z, p, q);
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}
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void EightBit::Intel8080::execute(const int x, const int y, const int z, const int p, const int q) {
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switch (x) {
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case 0:
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switch (z) {
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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tick(4);
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q) {
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case 0: // LD rp,nn
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RP(p) = fetchWord();
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tick(10);
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break;
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case 1: // ADD HL,rp
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add(RP(p));
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tick(11);
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 2: // Indirect loading
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switch (q) {
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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IntelProcessor::memoryWrite(BC(), A());
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tick(7);
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break;
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case 1: // LD (DE),A
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IntelProcessor::memoryWrite(DE(), A());
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tick(7);
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break;
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case 2: // LD (nn),HL
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BUS().ADDRESS() = fetchWord();
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setWord(HL());
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tick(16);
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break;
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case 3: // LD (nn),A
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BUS().ADDRESS() = fetchWord();
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IntelProcessor::memoryWrite(A());
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tick(13);
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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A() = IntelProcessor::memoryRead(BC());
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tick(7);
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break;
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case 1: // LD A,(DE)
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A() = IntelProcessor::memoryRead(DE());
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tick(7);
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break;
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case 2: // LD HL,(nn)
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BUS().ADDRESS() = fetchWord();
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HL() = getWord();
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tick(16);
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break;
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case 3: // LD A,(nn)
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BUS().ADDRESS() = fetchWord();
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A() = memoryRead();
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tick(13);
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break;
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default:
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UNREACHABLE;
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}
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q) {
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case 0: // INC rp
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++RP(p);
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break;
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case 1: // DEC rp
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--RP(p);
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break;
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default:
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UNREACHABLE;
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}
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tick(6);
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break;
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case 4: { // 8-bit INC
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auto operand = R(y);
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increment(operand);
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R(y, operand);
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tick(4);
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break;
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} case 5: { // 8-bit DEC
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auto operand = R(y);
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decrement(operand);
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R(y, operand);
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tick(4);
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if (UNLIKELY(y == 6))
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tick(7);
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break;
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} case 6: // 8-bit load immediate
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R(y, fetchByte());
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tick(7);
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if (UNLIKELY(y == 6))
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tick(3);
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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case 0:
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rlc();
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break;
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case 1:
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rrc();
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break;
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case 2:
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rl();
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break;
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case 3:
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rr();
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break;
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case 4:
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daa();
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break;
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case 5:
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cma();
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break;
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case 6:
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stc();
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break;
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case 7:
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cmc();
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break;
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default:
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UNREACHABLE;
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}
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tick(4);
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 1: // 8-bit loading
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if (UNLIKELY(z == 6 && y == 6)) { // Exception (replaces LD (HL), (HL))
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lowerHALT();
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} else {
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R(y, R(z));
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if (UNLIKELY((y == 6) || (z == 6))) // M operations
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tick(3);
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}
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tick(4);
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break;
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case 2: // Operate on accumulator and register/memory location
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switch (y) {
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case 0: // ADD A,r
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add(R(z));
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break;
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case 1: // ADC A,r
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adc(R(z));
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break;
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case 2: // SUB r
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subtract(A(), R(z));
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break;
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case 3: // SBC A,r
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sbb(R(z));
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break;
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case 4: // AND r
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andr(R(z));
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break;
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case 5: // XOR r
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xorr(R(z));
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break;
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case 6: // OR r
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orr(R(z));
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break;
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case 7: // CP r
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compare(R(z));
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break;
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default:
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UNREACHABLE;
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}
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tick(4);
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if (UNLIKELY(z == 6))
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tick(3);
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break;
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case 3:
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switch (z) {
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case 0: // Conditional return
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if (returnConditionalFlag(y))
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tick(6);
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tick(5);
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break;
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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RP2(p) = popWord();
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tick(10);
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break;
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case 1:
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switch (p) {
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case 0: // RET
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ret();
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tick(10);
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break;
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case 2: // JP HL
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jump(HL());
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tick(4);
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break;
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case 3: // LD SP,HL
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SP() = HL();
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tick(4);
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break;
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}
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break;
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default:
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UNREACHABLE;
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}
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break;
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case 2: // Conditional jump
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jumpConditionalFlag(y);
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tick(10);
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break;
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case 3: // Assorted operations
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switch (y) {
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case 0: // JP nn
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jump(fetchWord());
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tick(10);
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break;
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case 2: // OUT (n),A
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portWrite(fetchByte());
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tick(11);
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break;
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case 3: // IN A,(n)
|
|
A() = portRead(fetchByte());
|
|
tick(11);
|
|
break;
|
|
case 4: // EX (SP),HL
|
|
xhtl(HL());
|
|
tick(19);
|
|
break;
|
|
case 5: // EX DE,HL
|
|
std::swap(DE(), HL());
|
|
tick(4);
|
|
break;
|
|
case 6: // DI
|
|
di();
|
|
tick(4);
|
|
break;
|
|
case 7: // EI
|
|
ei();
|
|
tick(4);
|
|
break;
|
|
}
|
|
break;
|
|
case 4: // Conditional call: CALL cc[y], nn
|
|
if (callConditionalFlag(y))
|
|
tick(7);
|
|
tick(10);
|
|
break;
|
|
case 5: // PUSH & various ops
|
|
switch (q) {
|
|
case 0: // PUSH rp2[p]
|
|
pushWord(RP2(p));
|
|
tick(11);
|
|
break;
|
|
case 1:
|
|
switch (p) {
|
|
case 0: // CALL nn
|
|
call(fetchWord());
|
|
tick(17);
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
break;
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
switch (y) {
|
|
case 0: // ADD A,n
|
|
add(fetchByte());
|
|
break;
|
|
case 1: // ADC A,n
|
|
adc(fetchByte());
|
|
break;
|
|
case 2: // SUB n
|
|
subtract(A(), fetchByte());
|
|
break;
|
|
case 3: // SBC A,n
|
|
sbb(fetchByte());
|
|
break;
|
|
case 4: // AND n
|
|
andr(fetchByte());
|
|
break;
|
|
case 5: // XOR n
|
|
xorr(fetchByte());
|
|
break;
|
|
case 6: // OR n
|
|
orr(fetchByte());
|
|
break;
|
|
case 7: // CP n
|
|
compare(fetchByte());
|
|
break;
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
tick(7);
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
restart(y << 3);
|
|
tick(11);
|
|
break;
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
break;
|
|
}
|
|
}
|