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https://github.com/MoleskiCoder/EightBit.git
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459 lines
13 KiB
C++
459 lines
13 KiB
C++
#pragma once
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#include <cstdint>
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#include <cassert>
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#include <stdexcept>
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#include <Bus.h>
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#include <IntelProcessor.h>
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#include <EventArgs.h>
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#include <Signal.h>
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#include <Register.h>
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#include <EightBitCompilerDefinitions.h>
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namespace EightBit {
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class Z80 final : public IntelProcessor {
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public:
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struct refresh_t {
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bool high : 1;
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uint8_t variable : 7;
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refresh_t(const uint8_t value)
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: high(!!(value & Bit7)),
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variable(value & Mask7)
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{ }
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operator uint8_t() const {
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return (high << 7) | variable;
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}
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auto& operator++() {
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++variable;
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return *this;
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}
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};
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enum StatusBits {
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SF = Bit7,
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ZF = Bit6,
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YF = Bit5,
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HC = Bit4,
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XF = Bit3,
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PF = Bit2,
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VF = Bit2,
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NF = Bit1,
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CF = Bit0,
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};
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Z80(Bus& bus);
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Signal<Z80> ExecutingInstruction;
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Signal<Z80> ExecutedInstruction;
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int execute() final;
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int step() final;
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[[nodiscard]] register16_t& AF() final;
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[[nodiscard]] register16_t& BC() final;
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[[nodiscard]] register16_t& DE() final;
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[[nodiscard]] register16_t& HL() final;
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[[nodiscard]] auto& IX() { return m_ix; }
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[[nodiscard]] auto& IXH() { return IX().high; }
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[[nodiscard]] auto& IXL() { return IX().low; }
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[[nodiscard]] auto& IY() { return m_iy; }
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[[nodiscard]] auto& IYH() { return IY().high; }
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[[nodiscard]] auto& IYL() { return IY().low; }
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// ** From the Z80 CPU User Manual
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// Memory Refresh(R) Register.The Z80 CPU contains a memory refresh counter,
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// enabling dynamic memories to be used with the same ease as static memories.Seven bits
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// of this 8-bit register are automatically incremented after each instruction fetch.The eighth
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// bit remains as programmed, resulting from an LD R, A instruction. The data in the refresh
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// counter is sent out on the lower portion of the address bus along with a refresh control
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// signal while the CPU is decoding and executing the fetched instruction. This mode of refresh
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// is transparent to the programmer and does not slow the CPU operation.The programmer
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// can load the R register for testing purposes, but this register is normally not used by the
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// programmer. During refresh, the contents of the I Register are placed on the upper eight
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// bits of the address bus.
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[[nodiscard]] auto& REFRESH() { return m_refresh; }
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[[nodiscard]] auto& IV() { return iv; }
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[[nodiscard]] auto& IM() { return m_interruptMode; }
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[[nodiscard]] auto& IFF1() { return m_iff1; }
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[[nodiscard]] auto& IFF2() { return m_iff2; }
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void exx() {
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m_registerSet ^= 1;
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}
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void exxAF() {
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m_accumulatorFlagsSet ^= 1;
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}
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bool requestingIO() { return lowered(IORQ()); }
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bool requestingMemory() { return lowered(MREQ()); }
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bool requestingRead() { return lowered(RD()); }
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bool requestingWrite() { return lowered(WR()); }
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DECLARE_PIN_INPUT(NMI)
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DECLARE_PIN_OUTPUT(M1)
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// ** From the Z80 CPU User Manual
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// RFSH.Refresh(output, active Low). RFSH, together with MREQ, indicates that the lower
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// seven bits of the system<65>s address bus can be used as a refresh address to the system<65>s
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// dynamic memories.
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DECLARE_PIN_OUTPUT(RFSH)
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DECLARE_PIN_OUTPUT(MREQ)
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DECLARE_PIN_OUTPUT(IORQ)
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DECLARE_PIN_OUTPUT(RD)
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DECLARE_PIN_OUTPUT(WR)
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protected:
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void handleRESET() final;
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void handleINT() final;
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void pushWord(const register16_t destination) override {
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tick();
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IntelProcessor::pushWord(destination);
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}
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void memoryWrite() final;
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uint8_t memoryRead() final;
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void busWrite() final;
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uint8_t busRead() final;
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private:
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enum { BC_IDX, DE_IDX, HL_IDX };
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std::array<std::array<register16_t, 3>, 2> m_registers;
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int m_registerSet = 0;
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std::array<register16_t, 2> m_accumulatorFlags;
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int m_accumulatorFlagsSet = 0;
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register16_t m_ix = 0xffff;
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register16_t m_iy = 0xffff;
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refresh_t m_refresh = 0x7f;
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uint8_t iv = 0xff;
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int m_interruptMode = 0;
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bool m_iff1 = false;
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bool m_iff2 = false;
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bool m_prefixCB = false;
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bool m_prefixDD = false;
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bool m_prefixED = false;
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bool m_prefixFD = false;
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int8_t m_displacement = 0;
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bool m_displaced = false;
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void handleNMI();
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[[nodiscard]] uint16_t displacedAddress() {
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assert(m_displaced);
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return MEMPTR().word = (m_prefixDD ? IX() : IY()).word + m_displacement;
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}
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void fetchDisplacement() {
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m_displacement = fetchByte();
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}
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// ** From the Z80 CPU User Manual
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// Figure 5 depicts the timing during an M1 (op code fetch) cycle. The Program Counter is
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// placed on the address bus at the beginning of the M1 cycle. One half clock cycle later, the
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// MREQ signal goes active. At this time, the address to memory has had time to stabilize so
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// that the falling edge of MREQ can be used directly as a chip enable clock to dynamic
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// memories. The RD line also goes active to indicate that the memory read data should be
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// enabled onto the CPU data bus. The CPU samples the data from the memory space on the
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// data bus with the rising edge of the clock of state T3, and this same edge is used by the
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// CPU to turn off the RD and MREQ signals. As a result, the data is sampled by the CPU
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// before the RD signal becomes inactive. Clock states T3 and T4 of a fetch cycle are used to
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// refresh dynamic memories. The CPU uses this time to decode and execute the fetched
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// instruction so that no other concurrent operation can be performed.
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uint8_t readInitialOpCode() {
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tick();
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lowerM1();
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const auto returned = IntelProcessor::memoryRead(PC());
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raiseM1();
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BUS().ADDRESS() = { REFRESH(), IV() };
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lowerRFSH();
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lowerMREQ();
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raiseMREQ();
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raiseRFSH();
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return returned;
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}
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uint8_t fetchInitialOpCode() {
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const auto returned = readInitialOpCode();
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++PC();
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return returned;
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}
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[[nodiscard]] auto& HL2() {
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if (LIKELY(!m_displaced))
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return HL();
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if (m_prefixDD)
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return IX();
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// Must be FD prefix
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return IY();
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}
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[[nodiscard]] auto& RP(const int rp) {
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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switch (rp) {
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case 0:
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return BC();
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case 1:
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return DE();
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case 2:
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return HL2();
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case 3:
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return SP();
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default:
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UNREACHABLE;
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}
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}
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[[nodiscard]] auto& RP2(const int rp) {
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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switch (rp) {
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case 0:
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return BC();
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case 1:
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return DE();
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case 2:
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return HL2();
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case 3:
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return AF();
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default:
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UNREACHABLE;
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}
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}
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[[nodiscard]] auto R(const int r) {
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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switch (r) {
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case 0:
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return B();
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case 1:
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return C();
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case 2:
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return D();
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case 3:
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return E();
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case 4:
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return HL2().high;
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case 5:
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return HL2().low;
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case 6:
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return IntelProcessor::memoryRead(UNLIKELY(m_displaced) ? displacedAddress() : HL().word);
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case 7:
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return A();
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default:
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UNREACHABLE;
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}
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}
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void R(const int r, const uint8_t value) {
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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switch (r) {
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case 0:
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B() = value;
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break;
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case 1:
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C() = value;
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break;
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case 2:
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D() = value;
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break;
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case 3:
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E() = value;
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break;
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case 4:
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HL2().high = value;
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break;
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case 5:
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HL2().low = value;
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break;
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case 6:
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IntelProcessor::memoryWrite(UNLIKELY(m_displaced) ? displacedAddress() : HL().word, value);
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break;
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case 7:
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A() = value;
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break;
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default:
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UNREACHABLE;
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}
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}
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void R2(const int r, const uint8_t value) {
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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switch (r) {
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case 0:
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B() = value;
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break;
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case 1:
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C() = value;
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break;
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case 2:
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D() = value;
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break;
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case 3:
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E() = value;
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break;
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case 4:
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H() = value;
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break;
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case 5:
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L() = value;
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break;
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case 6:
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IntelProcessor::memoryWrite(HL(), value);
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break;
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case 7:
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A() = value;
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break;
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default:
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UNREACHABLE;
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}
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}
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[[nodiscard]] static uint8_t adjustHalfCarryAdd(uint8_t f, const uint8_t before, const uint8_t value, const int calculation) {
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return setBit(f, HC, calculateHalfCarryAdd(before, value, calculation));
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}
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[[nodiscard]] static uint8_t adjustHalfCarrySub(uint8_t f, const uint8_t before, const uint8_t value, const int calculation) {
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return setBit(f, HC, calculateHalfCarrySub(before, value, calculation));
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}
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[[nodiscard]] static uint8_t adjustOverflowAdd(uint8_t f, const uint8_t before, const uint8_t value, const uint8_t calculation) {
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return adjustOverflowAdd(f, before & SF, value & SF, calculation & SF);
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}
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[[nodiscard]] static uint8_t adjustOverflowAdd(uint8_t f, const int beforeNegative, const int valueNegative, const int afterNegative) {
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const auto overflow = (beforeNegative == valueNegative) && (beforeNegative != afterNegative);
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return setBit(f, VF, overflow);
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}
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[[nodiscard]] static uint8_t adjustOverflowSub(uint8_t f, const uint8_t before, const uint8_t value, const uint8_t calculation) {
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return adjustOverflowSub(f, before & SF, value & SF, calculation & SF);
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}
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[[nodiscard]] static uint8_t adjustOverflowSub(uint8_t f, const int beforeNegative, const int valueNegative, const int afterNegative) {
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const auto overflow = (beforeNegative != valueNegative) && (beforeNegative != afterNegative);
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return setBit(f, VF, overflow);
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}
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[[nodiscard]] static bool convertCondition(uint8_t f, int flag);
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static uint8_t subtract(uint8_t& f, uint8_t operand, uint8_t value, int carry = 0);
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void executeCB(int x, int y, int z);
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void executeED(int x, int y, int z, int p, int q);
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void executeOther(int x, int y, int z, int p, int q);
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[[nodiscard]] static uint8_t increment(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t decrement(uint8_t& f, uint8_t operand);
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void di();
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void ei();
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void retn();
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void reti();
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void returnConditionalFlag(uint8_t f, int flag);
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void jrConditionalFlag(uint8_t f, int flag);
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void callConditionalFlag(uint8_t f, int flag);
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void jumpConditionalFlag(uint8_t f, int flag);
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[[nodiscard]] register16_t sbc(uint8_t& f, register16_t operand, register16_t value);
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[[nodiscard]] register16_t adc(uint8_t& f, register16_t operand, register16_t value);
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[[nodiscard]] register16_t add(uint8_t& f, register16_t operand, register16_t value, int carry = 0);
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[[nodiscard]] static uint8_t add(uint8_t& f, uint8_t operand, uint8_t value, int carry = 0);
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[[nodiscard]] static uint8_t adc(uint8_t& f, uint8_t operand, uint8_t value);
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[[nodiscard]] static uint8_t sub(uint8_t& f, uint8_t operand, uint8_t value, int carry = 0);
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[[nodiscard]] static uint8_t sbc(uint8_t& f, uint8_t operand, uint8_t value);
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[[nodiscard]] static uint8_t andr(uint8_t& f, uint8_t operand, uint8_t value);
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[[nodiscard]] static uint8_t xorr(uint8_t& f, uint8_t operand, uint8_t value);
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[[nodiscard]] static uint8_t orr(uint8_t& f, uint8_t operand, uint8_t value);
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static void compare(uint8_t& f, uint8_t operand, uint8_t value);
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[[nodiscard]] static uint8_t rlc(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t rrc(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t rl(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t rr(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t sla(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t sra(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t sll(uint8_t& f, uint8_t operand);
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[[nodiscard]] static uint8_t srl(uint8_t& f, uint8_t operand);
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static void bit(uint8_t& f, int n, uint8_t operand);
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[[nodiscard]] static uint8_t res(int n, uint8_t operand);
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[[nodiscard]] static uint8_t set(int n, uint8_t operand);
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[[nodiscard]] static uint8_t daa(uint8_t& f, uint8_t operand);
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static void scf(uint8_t& f, uint8_t operand);
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static void ccf(uint8_t& f, uint8_t operand);
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static uint8_t cpl(uint8_t& f, uint8_t operand);
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void xhtl(register16_t& exchange);
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void blockCompare(uint8_t& f, uint8_t value, register16_t source, register16_t& counter);
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void cpi(uint8_t& f, uint8_t value);
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bool cpir(uint8_t& f, uint8_t value);
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void cpd(uint8_t& f, uint8_t value);
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bool cpdr(uint8_t& f, uint8_t value);
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void blockLoad(uint8_t& f, uint8_t a, register16_t source, register16_t destination, register16_t& counter);
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void ldi(uint8_t& f, uint8_t a);
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bool ldir(uint8_t& f, uint8_t a);
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void ldd(uint8_t& f, uint8_t a);
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bool lddr(uint8_t& f, uint8_t a);
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void blockIn(register16_t& source, register16_t destination);
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void ini();
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bool inir();
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void ind();
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bool indr();
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void blockOut(register16_t source, register16_t& destination);
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void outi();
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bool otir();
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void outd();
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bool otdr();
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[[nodiscard]] uint8_t neg(uint8_t& f, uint8_t operand);
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void rrd(uint8_t& f, register16_t address, uint8_t& update);
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void rld(uint8_t& f, register16_t address, uint8_t& update);
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void portWrite(uint8_t port);
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void portWrite();
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uint8_t portRead(uint8_t port);
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uint8_t portRead();
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};
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} |