mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2024-11-19 02:08:25 +00:00
666 lines
15 KiB
C++
666 lines
15 KiB
C++
#pragma once
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// Auxiliary carry logic from https://github.com/begoon/i8080-core
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#include "IntelProcessor.h"
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#include "InputOutput.h"
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namespace EightBit {
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class Intel8080 : public IntelProcessor {
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public:
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typedef std::function<void()> instruction_t;
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enum StatusBits {
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SF = Bit7,
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ZF = Bit6,
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AC = Bit4,
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PF = Bit2,
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CF = Bit0,
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};
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enum AddressingMode {
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Unknown,
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Implied, // zero bytes
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Immediate, // single byte
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Absolute // two bytes, little endian
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};
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struct Instruction {
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instruction_t vector = nullptr;
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AddressingMode mode = Unknown;
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std::string disassembly;
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int count = 0;
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};
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Intel8080(Memory& memory, InputOutput& ports);
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Signal<Intel8080> ExecutingInstruction;
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const std::array<Instruction, 0x100>& getInstructions() const { return instructions; }
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virtual register16_t& AF() override { return af; }
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virtual register16_t& BC() override { return bc; }
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virtual register16_t& DE() override { return de; }
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virtual register16_t& HL() override { return hl; }
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bool isInterruptable() const {
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return m_interrupt;
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}
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int interrupt(uint8_t value) {
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if (isInterruptable()) {
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di();
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return execute(value);
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}
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return 0;
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}
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virtual void initialise();
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int step();
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private:
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InputOutput& m_ports;
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std::array<Instruction, 0x100> instructions;
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register16_t af;
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register16_t bc;
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register16_t de;
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register16_t hl;
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bool m_interrupt;
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int execute(uint8_t opcode);
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int execute(const Instruction& instruction) {
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cycles = 0;
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instruction.vector();
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return cycles + instruction.count;
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}
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void adjustReservedFlags() {
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F() = (F() | Bit1) & ~(Bit5 | Bit3);
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}
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static void adjustAuxiliaryCarryAdd(uint8_t& f, uint8_t before, uint8_t value, int calculation) {
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setFlag(f, AC, calculateHalfCarryAdd(before, value, calculation));
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}
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static void adjustAuxiliaryCarrySub(uint8_t& f, uint8_t before, uint8_t value, int calculation) {
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clearFlag(f, AC, calculateHalfCarrySub(before, value, calculation));
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}
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static void postIncrement(uint8_t& f, uint8_t value) {
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adjustSZP<Intel8080>(f, value);
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clearFlag(f, AC, lowNibble(value));
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}
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static void postDecrement(uint8_t& f, uint8_t value) {
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adjustSZP<Intel8080>(f, value);
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setFlag(f, AC, lowNibble(value) != Mask4);
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}
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static Instruction INS(instruction_t method, AddressingMode mode, std::string disassembly, int cycles);
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Instruction UNKNOWN();
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void installInstructions();
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//
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void compare(uint8_t value) {
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auto check = A();
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sub(check, value);
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}
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void anda(uint8_t value) {
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auto& a = A();
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auto& f = F();
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setFlag(f, AC, (a | value) & Bit3);
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clearFlag(f, CF);
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adjustSZP<Intel8080>(f, a &= value);
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}
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void ora(uint8_t value) {
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auto& f = F();
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clearFlag(f, AC | CF);
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adjustSZP<Intel8080>(f, A() |= value);
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}
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void xra(uint8_t value) {
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auto& f = F();
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clearFlag(f, AC | CF);
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adjustSZP<Intel8080>(f, A() ^= value);
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}
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void add(uint8_t value, int carry = 0) {
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auto& a = A();
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auto& f = F();
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register16_t sum;
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sum.word = a + value + carry;
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adjustAuxiliaryCarryAdd(f, a, value, sum.word);
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a = sum.low;
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setFlag(f, CF, sum.word & Bit8);
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adjustSZP<Intel8080>(f, a);
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}
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void adc(uint8_t value) {
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add(value, F() & CF);
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}
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void dad(uint16_t value) {
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auto& f = F();
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auto sum = HL().word + value;
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setFlag(f, CF, sum & Bit16);
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HL().word = sum;
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}
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void sub(uint8_t& operand, uint8_t value, int carry = 0) {
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auto& f = F();
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register16_t difference;
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difference.word = operand - value - carry;
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adjustAuxiliaryCarrySub(f, operand, value, difference.word);
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operand = difference.low;
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setFlag(f, CF, difference.word & Bit8);
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adjustSZP<Intel8080>(f, operand);
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}
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void sub(uint8_t value, int carry = 0) {
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sub(A(), value, carry);
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}
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void sbb(uint8_t value) {
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sub(value, F() & CF);
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}
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void mov_m_r(uint8_t value) {
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m_memory.ADDRESS() = HL();
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m_memory.reference() = value;
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}
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uint8_t mov_r_m() {
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m_memory.ADDRESS() = HL();
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return m_memory.reference();
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}
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//
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void ___();
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// Move, load, and store
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void mov_a_a() { }
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void mov_a_b() { A() = B(); }
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void mov_a_c() { A() = C(); }
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void mov_a_d() { A() = D(); }
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void mov_a_e() { A() = E(); }
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void mov_a_h() { A() = H(); }
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void mov_a_l() { A() = L(); }
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void mov_b_a() { B() = A(); }
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void mov_b_b() { }
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void mov_b_c() { B() = C(); }
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void mov_b_d() { B() = D(); }
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void mov_b_e() { B() = E(); }
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void mov_b_h() { B() = H(); }
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void mov_b_l() { B() = L(); }
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void mov_c_a() { C() = A(); }
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void mov_c_b() { C() = B(); }
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void mov_c_c() { }
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void mov_c_d() { C() = D(); }
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void mov_c_e() { C() = E(); }
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void mov_c_h() { C() = H(); }
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void mov_c_l() { C() = L(); }
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void mov_d_a() { D() = A(); }
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void mov_d_b() { D() = B(); }
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void mov_d_c() { D() = C(); }
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void mov_d_d() { }
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void mov_d_e() { D() = E(); }
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void mov_d_h() { D() = H(); }
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void mov_d_l() { D() = L(); }
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void mov_e_a() { E() = A(); }
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void mov_e_b() { E() = B(); }
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void mov_e_c() { E() = C(); }
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void mov_e_d() { E() = D(); }
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void mov_e_e() { }
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void mov_e_h() { E() = H(); }
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void mov_e_l() { E() = L(); }
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void mov_h_a() { H() = A(); }
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void mov_h_b() { H() = B(); }
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void mov_h_c() { H() = C(); }
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void mov_h_d() { H() = D(); }
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void mov_h_e() { H() = E(); }
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void mov_h_h() { }
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void mov_h_l() { H() = L(); }
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void mov_l_a() { L() = A(); }
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void mov_l_b() { L() = B(); }
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void mov_l_c() { L() = C(); }
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void mov_l_d() { L() = D(); }
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void mov_l_e() { L() = E(); }
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void mov_l_h() { L() = H(); }
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void mov_l_l() { }
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void mov_m_a() { mov_m_r(A()); }
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void mov_m_b() { mov_m_r(B()); }
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void mov_m_c() { mov_m_r(C()); }
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void mov_m_d() { mov_m_r(D()); }
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void mov_m_e() { mov_m_r(E()); }
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void mov_m_h() { mov_m_r(H()); }
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void mov_m_l() { mov_m_r(L()); }
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void mov_a_m() { A() = mov_r_m(); }
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void mov_b_m() { B() = mov_r_m(); }
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void mov_c_m() { C() = mov_r_m(); }
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void mov_d_m() { D() = mov_r_m(); }
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void mov_e_m() { E() = mov_r_m(); }
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void mov_h_m() { H() = mov_r_m(); }
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void mov_l_m() { L() = mov_r_m(); }
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void mvi_a() { A() = fetchByte(); }
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void mvi_b() { B() = fetchByte(); }
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void mvi_c() { C() = fetchByte(); }
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void mvi_d() { D() = fetchByte(); }
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void mvi_e() { E() = fetchByte(); }
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void mvi_h() { H() = fetchByte(); }
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void mvi_l() { L() = fetchByte(); }
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void mvi_m() {
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auto data = fetchByte();
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m_memory.ADDRESS() = HL();
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m_memory.reference() = data;
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}
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void lxi_b() { fetchWord(BC()); }
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void lxi_d() { fetchWord(DE()); }
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void lxi_h() { fetchWord(HL()); }
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void stax_r(register16_t& destination) {
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m_memory.ADDRESS() = destination;
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m_memory.reference() = A();
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}
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void stax_b() { stax_r(BC()); }
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void stax_d() { stax_r(DE()); }
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void ldax_r(register16_t& source) {
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m_memory.ADDRESS() = source;
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A() = m_memory.reference();
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}
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void ldax_b() { ldax_r(BC()); }
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void ldax_d() { ldax_r(DE()); }
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void sta() {
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fetchWord();
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memptrReference() = A();
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}
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void lda() {
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fetchWord();
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A() = memptrReference();
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}
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void shld() {
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fetchWord();
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setWordViaMemptr(HL());
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}
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void lhld() {
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fetchWord();
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getWordViaMemptr(HL());
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}
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void xchg() {
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std::swap(DE(), HL());
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}
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// stack ops
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void push_b() { pushWord(BC()); }
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void push_d() { pushWord(DE()); }
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void push_h() { pushWord(HL()); }
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void push_psw() { pushWord(AF()); }
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void pop_b() { popWord(BC()); }
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void pop_d() { popWord(DE()); }
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void pop_h() { popWord(HL()); }
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void pop_psw() {
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popWord(AF());
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adjustReservedFlags();
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}
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void xhtl() {
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m_memory.ADDRESS() = SP();
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MEMPTR().low = m_memory.reference();
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m_memory.reference() = L();
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L() = MEMPTR().low;
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m_memory.ADDRESS().word++;
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MEMPTR().high = m_memory.reference();
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m_memory.reference() = H();
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H() = MEMPTR().high;
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}
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void sphl() {
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SP() = HL();
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}
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void lxi_sp() {
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fetchWord(SP());
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}
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void inx_sp() { ++SP().word; }
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void dcx_sp() { --SP().word; }
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// jump
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void jmp() { jumpConditional(true); }
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void jc() { jumpConditional(F() & CF); }
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void jnc() { jumpConditional(!(F() & CF)); }
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void jz() { jumpConditional(F() & ZF); }
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void jnz() { jumpConditional(!(F() & ZF)); }
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void jpe() { jumpConditional(F() & PF); }
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void jpo() { jumpConditional(!(F() & PF)); }
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void jm() { jumpConditional(F() & SF); }
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void jp() { jumpConditional(!(F() & SF)); }
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void pchl() {
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PC() = HL();
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}
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// call
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void callDirect() {
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fetchWord();
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call();
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}
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void cc() { if (callConditional(F() & CF)) cycles += 6; }
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void cnc() { if (callConditional(!(F() & CF))) cycles += 6; }
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void cpe() { if (callConditional(F() & PF)) cycles += 6; }
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void cpo() { if (callConditional(!(F() & PF))) cycles += 6; }
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void cz() { if (callConditional(F() & ZF)) cycles += 6; }
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void cnz() { if (callConditional(!(F() & ZF))) cycles += 6; }
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void cm() { if (callConditional(F() & SF)) cycles += 6; }
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void cp() { if (callConditional(!(F() & SF))) cycles += 6; }
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// return
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void rc() { if (returnConditional(F() & CF)) cycles += 6; }
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void rnc() { if (returnConditional(!(F() & CF))) cycles += 6; }
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void rz() { if (returnConditional(F() & ZF)) cycles += 6; }
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void rnz() { if (returnConditional(!(F() & ZF))) cycles += 6; }
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void rpe() { if (returnConditional(F() & PF)) cycles += 6; }
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void rpo() { if (returnConditional(!(F() & PF))) cycles += 6; }
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void rm() { if (returnConditional(F() & SF)) cycles += 6; }
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void rp() { if (returnConditional(!(F() & SF))) cycles += 6; }
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// restart
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void rst_0() { restart(0 << 3); }
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void rst_1() { restart(1 << 3); }
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void rst_2() { restart(2 << 3); }
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void rst_3() { restart(3 << 3); }
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void rst_4() { restart(4 << 3); }
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void rst_5() { restart(5 << 3); }
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void rst_6() { restart(6 << 3); }
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void rst_7() { restart(7 << 3); }
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// increment and decrement
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void inr_a() { postIncrement(F(), ++A()); }
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void inr_b() { postIncrement(F(), ++B()); }
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void inr_c() { postIncrement(F(), ++C()); }
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void inr_d() { postIncrement(F(), ++D()); }
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void inr_e() { postIncrement(F(), ++E()); }
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void inr_h() { postIncrement(F(), ++H()); }
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void inr_l() { postIncrement(F(), ++L()); }
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void inr_m() {
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m_memory.ADDRESS() = HL();
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auto value = m_memory.reference();
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postIncrement(F(), ++value);
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m_memory.reference() = value;
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}
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void dcr_a() { postDecrement(F(), --A()); }
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void dcr_b() { postDecrement(F(), --B()); }
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void dcr_c() { postDecrement(F(), --C()); }
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void dcr_d() { postDecrement(F(), --D()); }
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void dcr_e() { postDecrement(F(), --E()); }
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void dcr_h() { postDecrement(F(), --H()); }
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void dcr_l() { postDecrement(F(), --L()); }
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void dcr_m() {
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m_memory.ADDRESS() = HL();
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auto value = m_memory.reference();
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postDecrement(F(), --value);
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m_memory.reference() = value;
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}
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void inx_b() { ++BC().word; }
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void inx_d() { ++DE().word; }
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void inx_h() { ++HL().word; }
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void dcx_b() { --BC().word; }
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void dcx_d() { --DE().word; }
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void dcx_h() { --HL().word; }
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// add
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void add_a() { add(A()); }
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void add_b() { add(B()); }
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void add_c() { add(C()); }
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void add_d() { add(D()); }
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void add_e() { add(E()); }
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void add_h() { add(H()); }
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void add_l() { add(L()); }
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void add_m() {
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m_memory.ADDRESS() = HL();
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add(m_memory.reference());
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}
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void adi() { add(fetchByte()); }
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void adc_a() { adc(A()); }
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void adc_b() { adc(B()); }
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void adc_c() { adc(C()); }
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void adc_d() { adc(D()); }
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void adc_e() { adc(E()); }
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void adc_h() { adc(H()); }
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void adc_l() { adc(L()); }
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void adc_m() {
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m_memory.ADDRESS() = HL();
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adc(m_memory.reference());
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}
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void aci() { adc(fetchByte()); }
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void dad_b() { dad(BC().word); }
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void dad_d() { dad(DE().word); }
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void dad_h() { dad(HL().word); }
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void dad_sp() { dad(SP().word); }
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// subtract
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void sub_a() { sub(A()); }
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void sub_b() { sub(B()); }
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void sub_c() { sub(C()); }
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void sub_d() { sub(D()); }
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void sub_e() { sub(E()); }
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void sub_h() { sub(H()); }
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void sub_l() { sub(L()); }
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void sub_m() {
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m_memory.ADDRESS() = HL();
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sub(m_memory.reference());
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}
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void sbb_a() { sbb(A()); }
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void sbb_b() { sbb(B()); }
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void sbb_c() { sbb(C()); }
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void sbb_d() { sbb(D()); }
|
|
void sbb_e() { sbb(E()); }
|
|
void sbb_h() { sbb(H()); }
|
|
void sbb_l() { sbb(L()); }
|
|
|
|
void sbb_m() {
|
|
m_memory.ADDRESS() = HL();
|
|
sbb(m_memory.reference());
|
|
}
|
|
|
|
void sbi() {
|
|
sbb(fetchByte());
|
|
}
|
|
|
|
void sui() {
|
|
sub(fetchByte());
|
|
}
|
|
|
|
// logical
|
|
|
|
void ana_a() { anda(A()); }
|
|
void ana_b() { anda(B()); }
|
|
void ana_c() { anda(C()); }
|
|
void ana_d() { anda(D()); }
|
|
void ana_e() { anda(E()); }
|
|
void ana_h() { anda(H()); }
|
|
void ana_l() { anda(L()); }
|
|
|
|
void ana_m() {
|
|
m_memory.ADDRESS() = HL();
|
|
anda(m_memory.reference());
|
|
}
|
|
|
|
void ani() { anda(fetchByte()); }
|
|
|
|
void xra_a() { xra(A()); }
|
|
void xra_b() { xra(B()); }
|
|
void xra_c() { xra(C()); }
|
|
void xra_d() { xra(D()); }
|
|
void xra_e() { xra(E()); }
|
|
void xra_h() { xra(H()); }
|
|
void xra_l() { xra(L()); }
|
|
|
|
void xra_m() {
|
|
m_memory.ADDRESS() = HL();
|
|
xra(m_memory.reference());
|
|
}
|
|
|
|
void xri() { xra(fetchByte()); }
|
|
|
|
void ora_a() { ora(A()); }
|
|
void ora_b() { ora(B()); }
|
|
void ora_c() { ora(C()); }
|
|
void ora_d() { ora(D()); }
|
|
void ora_e() { ora(E()); }
|
|
void ora_h() { ora(H()); }
|
|
void ora_l() { ora(L()); }
|
|
|
|
void ora_m() {
|
|
m_memory.ADDRESS() = HL();
|
|
ora(m_memory.reference());
|
|
}
|
|
|
|
void ori() { ora(fetchByte()); }
|
|
|
|
void cmp_a() { compare(A()); }
|
|
void cmp_b() { compare(B()); }
|
|
void cmp_c() { compare(C()); }
|
|
void cmp_d() { compare(D()); }
|
|
void cmp_e() { compare(E()); }
|
|
void cmp_h() { compare(H()); }
|
|
void cmp_l() { compare(L()); }
|
|
|
|
void cmp_m() {
|
|
m_memory.ADDRESS() = HL();
|
|
compare(m_memory.reference());
|
|
}
|
|
|
|
void cpi() { compare(fetchByte()); }
|
|
|
|
// rotate
|
|
|
|
void rlc() {
|
|
auto& a = A();
|
|
auto carry = a & Bit7;
|
|
a = (a << 1) | (carry >> 7);
|
|
setFlag(F(), CF, carry);
|
|
}
|
|
|
|
void rrc() {
|
|
auto& a = A();
|
|
auto carry = a & Bit0;
|
|
a = (a >> 1) | (carry << 7);
|
|
setFlag(F(), CF, carry);
|
|
}
|
|
|
|
void ral() {
|
|
auto& a = A();
|
|
auto& f = F();
|
|
const auto carry = f & CF;
|
|
setFlag(f, CF, a & Bit7);
|
|
a = (a << 1) | carry;
|
|
}
|
|
|
|
void rar() {
|
|
auto& a = A();
|
|
auto& f = F();
|
|
const auto carry = f & CF;
|
|
setFlag(f, CF, a & Bit0);
|
|
a = (a >> 1) | (carry << 7);
|
|
}
|
|
|
|
// specials
|
|
|
|
void cma() { A() ^= Mask8; }
|
|
void stc() { setFlag(F(), CF); }
|
|
void cmc() { clearFlag(F(), CF, F() & CF); }
|
|
|
|
void daa() {
|
|
const auto& a = A();
|
|
auto& f = F();
|
|
auto carry = f & CF;
|
|
uint8_t addition = 0;
|
|
if ((f & AC) || lowNibble(a) > 9) {
|
|
addition = 0x6;
|
|
}
|
|
if ((f & CF) || highNibble(a) > 9 || (highNibble(a) >= 9 && lowNibble(a) > 9)) {
|
|
addition |= 0x60;
|
|
carry = true;
|
|
}
|
|
add(addition);
|
|
setFlag(f, CF, carry);
|
|
}
|
|
|
|
// input/output
|
|
|
|
void out() { m_ports.write(fetchByte(), A()); }
|
|
void in() { A() = m_ports.read(fetchByte()); }
|
|
|
|
// control
|
|
|
|
void ei() { m_interrupt = true; }
|
|
void di() { m_interrupt = false; }
|
|
|
|
void nop() {}
|
|
|
|
void hlt() { halt(); }
|
|
};
|
|
} |