mirror of
https://github.com/MoleskiCoder/EightBit.git
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96 lines
4.7 KiB
C++
96 lines
4.7 KiB
C++
#pragma once
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#include <cstdint>
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#include <Processor.h>
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namespace EightBit {
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class mc6850 {
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public:
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// +--------+----------------------------------------------------------------------------------+
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// | | Buffer address |
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// | +------------------+------------------+--------------------+-----------------------+
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// | | _ | _ | _ | _ |
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// | Data | RS * R/W | RS * R/W | RS * R/W | RS * R/W |
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// | Bus | (high)(low) | (high)(high) | (low)(low) | (low)(low) |
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// | Line | Transmit | Receive | | |
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// | Number | Data | Data | Control | Control |
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// | | Register | Register | register | register |
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// | +------------------+------------------+--------------------+-----------------------+
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// | | (Write only) + (Read only) + (Write only) | (Read only) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 0 | Data bit 0* | Data bit 0 | Counter divide | Receive data register |
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// | | | | select 1 (CR0) | full (RDRF) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 1 | Data bit 1 | Data bit 1 | Counter divide | Transmit data register|
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// | | | | select 2 (CR1) | empty (TDRE) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 2 | Data bit 2 | Data bit 2 | Word select 1 | Data carrier detect |
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// | | | | (CR2) | (DCD active) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 3 | Data bit 3 | Data bit 3 | Word select 1 | Clear to send |
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// | | | | (CR3) | (CTS active) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 4 | Data bit 4 | Data bit 4 | Word select 1 | Framing error |
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// | | | | (CR4) | (FE) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 5 | Data bit 5 | Data bit 5 | Transmit control 1 | Receiver overrun |
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// | | | | (CR5) | (OVRN) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 6 | Data bit 6 | Data bit 6 | Transmit control 2 | Parity error (PE) |
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// | | | | (CR6) | ||
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// +--------+------------------+------------------+--------------------+-----------------------+
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// | 7 | Data bit 7*** | Data bit 7** | Receive interrupt | Interrupt request |
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// | | | | enable (CR7) | (IRQ active) |
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// +--------+------------------+------------------+--------------------+-----------------------+
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// * Leading bit = LSB = Bit 0
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// ** Data bit will be zero in 7-bit plus parity modes
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// *** Data bit is "don't case" in 7-bit plus parity modes
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Processor::PinLevel& RXDATA() { return m_RXDATA; } // Receive data, (I) Active high
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Processor::PinLevel& TXDATA() { return m_TXDATA; } // Transmit data, (O) Active high
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Processor::PinLevel& RTS() { return m_RTS; } // Request to send, (O) Active low
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Processor::PinLevel& CTS() { return m_CTS; } // Clear to send, (I) Active low
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Processor::PinLevel& DCD() { return m_DCD; } // Data carrier detect, (I) Active low
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Processor::PinLevel& RXCLK() { return m_RXCLK; } // Transmit clock, (I) Active high
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Processor::PinLevel& TXCLK() { return m_TXCLK; } // Receive clock, (I) Active high
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uint8_t& DATA() { return m_data; } // Data, (I/O)
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Processor::PinLevel& CS0() { return m_CS0; } // Chip select, bit 0, (I) Active high
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Processor::PinLevel& CS1() { return m_CS1; } // Chip select, bit 1, (I) Active high
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Processor::PinLevel& CS2() { return m_CS2; } // Chip select, bit 2, (I) Active low
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Processor::PinLevel& RS() { return m_RS; } // Register select, (I) Active high
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Processor::PinLevel& RW() { return m_RW; } // Read/Write, (I) Read high, write low
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Processor::PinLevel& E() { return m_E; } // ACIA Enable, (I) Active high
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Processor::PinLevel& IRQ() { return m_IRQ; } // Interrupt request, (O) Active low
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private:
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Processor::PinLevel m_RXDATA;
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Processor::PinLevel m_TXDATA;
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Processor::PinLevel m_RTS;
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Processor::PinLevel m_CTS;
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Processor::PinLevel m_DCD;
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Processor::PinLevel m_RXCLK;
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Processor::PinLevel m_TXCLK;
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uint8_t m_data;
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Processor::PinLevel m_CS0;
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Processor::PinLevel m_CS1;
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Processor::PinLevel m_CS2;
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Processor::PinLevel m_RS;
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Processor::PinLevel m_RW;
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Processor::PinLevel m_E;
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Processor::PinLevel m_IRQ;
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};
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}
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