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133 lines
5.4 KiB
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<title>Interrupt Behaviour of the Z80 CPU</title>
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<meta name="title" content="Thomas Scherrer Z80-Family HomePage">
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<meta name="author" content="Achim Flammenkamp">
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<a name="TOP">
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<h1> Interrupt Behaviour of the Z80 CPU</h1>
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<p><i>by Achim Flammenkamp</i></p>
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<h2>Interrupt timing</h2>
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Only at the end of an instruction execution, except a NOP in case HALT, a LDD in case LDDR, a OUTI in case OTIR, etc., the CPU checks for an interrupt request.
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Thus the INT-pin should be active for at least 23 clock ticks because some IX
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resp. IY instruction last so long.
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Now an interrupt is accepted if INT-pin is low(active) and the interrupt flip flop
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IFF1 is set or the NMI-pin is respectively was active during the just performed instruction.
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If this is the case, the following happens:<br>
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Immediately IFF1 is reset to 0 and if INT-pin is low also IFF2 is reset to 0.
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Then the behavior depends whether it is a non maskable interrupt (NMI) or a
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maskable interrupt (INT). In the later case the interrupt mode (IM) of the CPU is
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also decisive:
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<ul>
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<li>NMI<br>
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It takes 11 clock cycles to get to #0066:
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<ol>
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<li> M1 cycle: 5 T states to do an opcode read and decrement SP
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</li><li> M2 cycle: 3 T states write high byte of PC to the stack and decrement SP
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</li><li> M3 cycle: 3 T states write the low byte of PC and jump to #0066.
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</li></ol>
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</li><li>INT and interrupt mode 0 set<br>
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In this mode, timing depends on the instruction put on the bus.
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The interrupt processing last 2 clock cycles more
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than this instruction usually needs.<br>
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Two typical examples follow:<br>
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<ol>
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a RST n on the data bus, it takes 13 cycles to get to 'n':
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<li> M1 cycle: 7 ticks<br>acknowledge interrupt and decrement SP
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</li><li> M2 cycle: 3 ticks<br>write high byte and decrement SP
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</li><li> M3 cycle: 3 ticks<br>write low byte and jump to 'n'
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</li></ol>
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<ol>
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With a CALL nnnn on the data bus, it takes 19 cycles:
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<li> M1 cycle: 7 ticks<br>acknowledge interrupt
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</li><li> M2 cycle: 3 ticks<br>read low byte of 'nnnn' from data bus
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</li><li> M3 cycle: 3 ticks<br>read high byte of 'nnnn' and decrement SP
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</li><li> M4 cycle: 3 ticks<br>write high byte of PC to the stack and decrement SP
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</li><li> M5 cycle: 3 ticks<br>write low byte of PC and jump to 'nnnn'.
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</li></ol>
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</li><li>INT and interrupt mode 1 set<br>
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It takes 13 clock cycles to reach #0038:
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<ol>
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<li> M1 cycle: 7 ticks<br>
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acknowledge interrupt and decrement SP
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</li><li> M2 cycle: 3 ticks<br>
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write high byte of PC onto the stack and decrement SP
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</li><li> M3 cycle: 3 ticks<br>
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write low byte onto the stack and to set PC to #0038.
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</li></ol>
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</li><li>INT and interrupt mode 2 set<br>
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It takes 19 clock cycles to get to the interrupt routine:
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<ol>
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<li> M1 cycle: 7 ticks<br>
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acknowledge interrupt and decrement SP
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</li><li> M2 cycle: 3 ticks<br>
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write high byte of PC onto stack and decrement SP
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</li><li> M3 cycle: 3 ticks<br>
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write low byte onto the stack
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</li><li> M4 cycle: 3 ticks<br>
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read low byte from the interrupt vector
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</li><li> M5 cycle: 3 ticks<br>
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read high byte from bus and jump to interrupt routine
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</li></ol></li></ul>
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Some remarks:
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<ol>
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<li> "acknowledge interrupt" means pin IORQ gets together with M1-pin
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active/low. Furthermore the CPU adds 2 wait states to the normal machine cycle.
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</li><li>Quoted remark<em>:
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<ul>
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<li>If a LD A,I or LD A,R (which copy IFF2
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to the P/V flag) is interrupted, then the P/V flag is reset, even if
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interrupts were enabled beforehand.
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</li><li>If interrupts are disabled when a EI instruction is
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interrupted, then the interrupt will not occur until after the
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instruction following the EI, as when IFF1 is sampled
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during the one and only machine-cycle of the EI, it will be reset.
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</li></ul>
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</em>
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</li><li>An INT will let the INT-pin low(active) until it is indirectly
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reseted by an RETI or other external hardware. In contrast a signal
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at the NMI-pin will be recognized when its state going from high to low!
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Thus it is not a level trigger signal, but a pulse which is stored internally
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by the CPU until the next M1 cycle.
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</li></ol>
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<p>
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</p><h2>Reset Timing</h2>
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One can consider a reset (RESET-pin gets low) as a very special interrupt.
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If this occurs, the following happens in one machine cycle:<br>
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<ul>
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It takes 3 clock cycles:
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<li>IFF1 and IFF2 as well as interrupt mode is set to 0
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</li><li>PC is set to 0, I and R registers are reset also.
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</li><li>SP is set to 0xffff as well as the A and the F register is set to 0xff.
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</li></ul>
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<p>
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</p><h3>Thanks for contribution goes to:</h3>
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</a><ul><a name="TOP">
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<li>Z80 Family CPU User Manual
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</li><li>Sean Young (sean[AT]msxnet[DOT]org)
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</li></a><li><a name="TOP"></a><a href="http://www.nvg.ntnu.no/sinclair/faq/tech_z80.html">http://www.nvg.ntnu.no/sinclair/faq/tech_z80.html</a>
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</li><li>Mutt (redflame[AT]xmission[DOT]com)
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</li><li>Andrew Campbell (campbell[AT]comet[DOT]columbia[DOT]edu)
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</li></ul>
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<p></p>
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<hr>
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<a href="http://www.z80.info/index.htm">Back to main page</a>.
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