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Tidy register increment/decrement a little.

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This commit is contained in:
Adrian Conlon
2025-07-25 16:32:30 +01:00
parent c271b28495
commit 2f338c6c46
10 changed files with 68 additions and 58 deletions
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4
EightBit/BigEndianProcessor.cs
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@@ -28,7 +28,7 @@ namespace EightBit
protected override Register16 GetWord() protected override Register16 GetWord()
{ {
this.Intermediate.High = this.MemoryRead(); this.Intermediate.High = this.MemoryRead();
this.Bus.Address.Increment(); _ = this.Bus.Address.Increment();
this.Intermediate.Low = this.MemoryRead(); this.Intermediate.Low = this.MemoryRead();
return this.Intermediate; return this.Intermediate;
} }
@@ -57,7 +57,7 @@ namespace EightBit
protected override void SetWord(Register16 value) protected override void SetWord(Register16 value)
{ {
this.MemoryWrite(value.High); this.MemoryWrite(value.High);
this.Bus.Address.Increment(); _ = this.Bus.Address.Increment();
this.MemoryWrite(value.Low); this.MemoryWrite(value.Low);
} }

10
EightBit/IntelProcessor.cs
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@@ -100,12 +100,13 @@ namespace EightBit
protected abstract void EnableInterrupts(); protected abstract void EnableInterrupts();
protected override void IncrementPC() protected override Register16 IncrementPC()
{ {
if (this.HALT.Raised()) if (this.HALT.Raised())
{ {
base.IncrementPC(); return base.IncrementPC();
} }
return this.PC;
} }
protected override byte FetchInstruction() protected override byte FetchInstruction()
@@ -149,14 +150,13 @@ namespace EightBit
protected sealed override void Push(byte value) protected sealed override void Push(byte value)
{ {
this.SP.Decrement(); this.MemoryWrite(this.SP.Decrement(), value);
this.MemoryWrite(this.SP, value);
} }
protected sealed override byte Pop() protected sealed override byte Pop()
{ {
var returned = this.MemoryRead(this.SP); var returned = this.MemoryRead(this.SP);
this.SP.Increment(); _ = this.SP.Increment();
return returned; return returned;
} }

4
EightBit/LittleEndianProcessor.cs
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@@ -29,7 +29,7 @@ namespace EightBit
protected override Register16 GetWord() protected override Register16 GetWord()
{ {
this.Intermediate.Low = this.MemoryRead(); this.Intermediate.Low = this.MemoryRead();
this.Bus.Address.Increment(); _ = this.Bus.Address.Increment();
this.Intermediate.High = this.MemoryRead(); this.Intermediate.High = this.MemoryRead();
return this.Intermediate; return this.Intermediate;
} }
@@ -58,7 +58,7 @@ namespace EightBit
protected override void SetWord(Register16 value) protected override void SetWord(Register16 value)
{ {
this.MemoryWrite(value.Low); this.MemoryWrite(value.Low);
this.Bus.Address.Increment(); _ = this.Bus.Address.Increment();
this.MemoryWrite(value.High); this.MemoryWrite(value.High);
} }

6
EightBit/Processor.cs
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@@ -261,14 +261,14 @@ namespace EightBit
protected virtual byte BusRead() => this.Bus.Read(); // N.B. Should be the only real call into the "Bus.Read" code. protected virtual byte BusRead() => this.Bus.Read(); // N.B. Should be the only real call into the "Bus.Read" code.
protected virtual void IncrementPC() => this.PC.Increment(); protected virtual Register16 IncrementPC() => this.PC.Increment();
protected virtual void DecrementPC() => this.PC.Decrement(); protected virtual Register16 DecrementPC() => this.PC.Decrement();
protected virtual void ImmediateAddress() protected virtual void ImmediateAddress()
{ {
this.Bus.Address.Assign(this.PC); this.Bus.Address.Assign(this.PC);
this.IncrementPC(); _ = this.IncrementPC();
} }
protected virtual byte FetchByte() protected virtual byte FetchByte()

4
EightBit/Register16.cs
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@@ -95,14 +95,14 @@ namespace EightBit
[MethodImpl(MethodImplOptions.AggressiveInlining)] [MethodImpl(MethodImplOptions.AggressiveInlining)]
public Register16 Increment() public Register16 Increment()
{ {
this.Word++; ++this.Word;
return this; return this;
} }
[MethodImpl(MethodImplOptions.AggressiveInlining)] [MethodImpl(MethodImplOptions.AggressiveInlining)]
public Register16 Decrement() public Register16 Decrement()
{ {
this.Word--; --this.Word;
return this; return this;
} }
} }

8
Intel8080/Intel8080.cs
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@@ -326,10 +326,10 @@ namespace Intel8080
switch (q) switch (q)
{ {
case 0: // INC rp case 0: // INC rp
this.RP(p).Increment(); _ = this.RP(p).Increment();
break; break;
case 1: // DEC rp case 1: // DEC rp
this.RP(p).Decrement(); _ = this.RP(p).Decrement();
break; break;
default: default:
throw new NotSupportedException("Invalid operation mode"); throw new NotSupportedException("Invalid operation mode");
@@ -757,11 +757,11 @@ namespace Intel8080
private void XHTL(Register16 exchange) private void XHTL(Register16 exchange)
{ {
this.MEMPTR.Low = this.MemoryRead(this.SP); this.MEMPTR.Low = this.MemoryRead(this.SP);
this.Bus.Address.Increment(); _ = this.Bus.Address.Increment();
this.MEMPTR.High = this.MemoryRead(); this.MEMPTR.High = this.MemoryRead();
this.MemoryWrite(exchange.High); this.MemoryWrite(exchange.High);
exchange.High = this.MEMPTR.High; exchange.High = this.MEMPTR.High;
this.Bus.Address.Decrement(); _ = this.Bus.Address.Decrement();
this.MemoryWrite(exchange.Low); this.MemoryWrite(exchange.Low);
exchange.Low = this.MEMPTR.Low; exchange.Low = this.MEMPTR.Low;
} }

2
LR35902/IoRegisters.cs
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@@ -150,7 +150,7 @@ namespace LR35902
public void IncrementDIV() public void IncrementDIV()
{ {
this.divCounter.Increment(); _ = this.divCounter.Increment();
this.Poke(DIV, this.divCounter.High); this.Poke(DIV, this.divCounter.High);
} }

58
LR35902/LR35902.cs
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@@ -553,36 +553,50 @@ namespace LR35902
switch (p) switch (p)
{ {
case 0: // LD (BC),A case 0: // LD (BC),A
this.MemoryWrite(this.BC, this.A); this.Bus.Address.Assign(this.BC);
break; break;
case 1: // LD (DE),A case 1: // LD (DE),A
this.MemoryWrite(this.DE, this.A); this.Bus.Address.Assign(this.DE);
break; break;
case 2: // GB: LDI (HL),A case 2: // GB: LDI (HL),A
this.MemoryWrite(this.HL.Increment(), this.A); this.Bus.Address.Assign(this.HL);
_ = this.HL.Increment();
break; break;
case 3: // GB: LDD (HL),A case 3: // GB: LDD (HL),A
this.MemoryWrite(this.HL.Decrement(), this.A); this.Bus.Address.Assign(this.HL);
_ = this.HL.Decrement();
break; break;
default: default:
throw new InvalidOperationException("Invalid operation mode"); throw new InvalidOperationException("Invalid operation mode");
} }
this.MemoryWrite(this.A);
break; break;
case 1: case 1:
this.A = p switch switch(p)
{ {
0 => this.MemoryRead(this.BC), // LD A,(BC) case 0: // LD A,(BC)
1 => this.MemoryRead(this.DE), // LD A,(DE) this.Bus.Address.Assign(this.BC);
2 => this.MemoryRead(this.HL.Increment()), // GB: LDI A,(HL) break;
3 => this.MemoryRead(this.HL.Decrement()), // GB: LDD A,(HL) case 1: // LD A,(DE)
_ => throw new InvalidOperationException("Invalid operation mode"), this.Bus.Address.Assign(this.DE);
}; break;
case 2: // GB: LDI A,(HL)
this.Bus.Address.Assign(this.HL);
_ = this.HL.Increment();
break;
case 3: // GB: LDD A,(HL)
this.Bus.Address.Assign(this.HL);
_ = this.HL.Decrement();
break;
default:
throw new InvalidOperationException("Invalid operation mode");
}
this.A = this.MemoryRead();
break; break;
default: default:
@@ -592,20 +606,14 @@ namespace LR35902
break; break;
case 3: // 16-bit INC/DEC case 3: // 16-bit INC/DEC
switch (q) _ = q switch
{ {
case 0: // INC rp // INC rp
this.RP(p).Increment(); 0 => this.RP(p).Increment(),
break; // DEC rp
1 => this.RP(p).Decrement(),
case 1: // DEC rp _ => throw new InvalidOperationException("Invalid operation mode"),
this.RP(p).Decrement(); };
break;
default:
throw new InvalidOperationException("Invalid operation mode");
}
this.TickMachine(); this.TickMachine();
break; break;

11
M6502/Core.cs
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@@ -599,16 +599,19 @@ namespace M6502
protected override byte FetchInstruction() protected override byte FetchInstruction()
{ {
this.LowerSYNC(); this.LowerSYNC();
try
{
System.Diagnostics.Debug.Assert(this.Cycles == 1, "An extra cycle has occurred"); System.Diagnostics.Debug.Assert(this.Cycles == 1, "An extra cycle has occurred");
// Can't use "FetchByte", since that would add an extra tick. // Can't use "FetchByte", since that would add an extra tick.
this.ImmediateAddress(); this.ImmediateAddress();
var returned = this.ReadFromBus(); return this.ReadFromBus();
}
finally
{
System.Diagnostics.Debug.Assert(this.Cycles == 1, "BUS read has introduced stray cycles"); System.Diagnostics.Debug.Assert(this.Cycles == 1, "BUS read has introduced stray cycles");
this.RaiseSYNC(); this.RaiseSYNC();
}
return returned;
} }
#endregion #endregion

9
Z80/Z80.cs
View File

@@ -2151,13 +2151,13 @@ namespace Z80
this.Bus.Address.Increment(); this.Bus.Address.Increment();
this.MEMPTR.High = this.MemoryRead(); this.MEMPTR.High = this.MemoryRead();
this.Tick(); this.Tick();
this.Bus.Address.Decrement(); _ = this.Bus.Address.Decrement();
this.Tick(); this.Tick();
this.Bus.Data = exchange.Low; this.Bus.Data = exchange.Low;
exchange.Low = this.MEMPTR.Low; exchange.Low = this.MEMPTR.Low;
this.MemoryUpdate(1); this.MemoryUpdate(1);
this.Tick(); this.Tick();
this.Bus.Address.Increment(); _ = this.Bus.Address.Increment();
this.Tick(); this.Tick();
this.Bus.Data = exchange.High; this.Bus.Data = exchange.High;
exchange.High = this.MEMPTR.High; exchange.High = this.MEMPTR.High;
@@ -2169,9 +2169,8 @@ namespace Z80
private void RepeatBlockInstruction() private void RepeatBlockInstruction()
{ {
this.DecrementPC(); this.MEMPTR.Assign(this.DecrementPC());
this.MEMPTR.Assign(this.PC); _ = this.DecrementPC();
this.DecrementPC();
this.AdjustXY(this.PC.High); this.AdjustXY(this.PC.High);
} }