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Share instruction fetch and halt implementations

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This commit is contained in:
Adrian Conlon
2025-05-04 11:41:28 +01:00
parent 2336222c97
commit 93e09c192f
6 changed files with 28 additions and 30 deletions
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7
EightBit/IntelProcessor.cs
View File

@@ -96,6 +96,13 @@ namespace EightBit
} }
} }
protected override byte FetchInstruction()
{
var read = this.FetchByte();
return this.HALT.Lowered() ? (byte)0 : read;
}
protected void ResetWorkingRegisters() protected void ResetWorkingRegisters()
{ {
this.AF.Word = this.BC.Word = this.DE.Word = this.HL.Word = (ushort)Mask.Sixteen; this.AF.Word = this.BC.Word = this.DE.Word = this.HL.Word = (ushort)Mask.Sixteen;

5
EightBit/Processor.cs
View File

@@ -92,6 +92,11 @@ namespace EightBit
return current; return current;
} }
protected virtual byte FetchInstruction()
{
return this.FetchByte();
}
public void Execute(byte value) public void Execute(byte value)
{ {
this.OpCode = value; this.OpCode = value;

7
Intel8080/Intel8080.cs
View File

@@ -54,14 +54,9 @@ namespace Intel8080
{ {
this.HandleINT(); this.HandleINT();
} }
else if (this.HALT.Lowered())
{
_ = this.FetchByte();
this.Execute(0); // NOP
}
else else
{ {
this.Execute(this.FetchByte()); this.Execute(this.FetchInstruction());
} }
} }

7
LR35902/LR35902.cs
View File

@@ -224,14 +224,9 @@ namespace LR35902
{ {
this.HandleINT(); this.HandleINT();
} }
else if (this.HALT.Lowered())
{
_ = this.FetchByte();
this.Execute(0); // NOP
}
else else
{ {
this.Execute(this.FetchByte()); this.Execute(this.FetchInstruction());
} }
} }

8
M6502/Core.cs
View File

@@ -516,7 +516,7 @@ namespace M6502
if (this.RDY.Raised()) if (this.RDY.Raised())
{ {
this.FetchInstruction(); this.OpCode = this.FetchInstruction();
if (this.RESET.Lowered()) if (this.RESET.Lowered())
{ {
this.HandleRESET(); this.HandleRESET();
@@ -536,17 +536,19 @@ namespace M6502
} }
} }
private void FetchInstruction() protected override byte FetchInstruction()
{ {
this.LowerSYNC(); this.LowerSYNC();
System.Diagnostics.Debug.Assert(this.Cycles == 1, "An extra cycle has occurred"); System.Diagnostics.Debug.Assert(this.Cycles == 1, "An extra cycle has occurred");
// Can't use "FetchByte", since that would add an extra tick. // Can't use "FetchByte", since that would add an extra tick.
this.ImmediateAddress(); this.ImmediateAddress();
this.OpCode = this.ReadFromBus(); var returned = this.ReadFromBus();
System.Diagnostics.Debug.Assert(this.Cycles == 1, "BUS read has introduced stray cycles"); System.Diagnostics.Debug.Assert(this.Cycles == 1, "BUS read has introduced stray cycles");
this.RaiseSYNC(); this.RaiseSYNC();
return returned;
} }
#endregion #endregion

24
Z80/Z80.cs
View File

@@ -142,7 +142,8 @@ namespace Z80
handled = true; handled = true;
} }
} }
else if (this.HALT.Lowered())
if (!handled)
{ {
// ** From the Z80 CPU User Manual // ** From the Z80 CPU User Manual
// When a software HALT instruction is executed, the CPU executes NOPs until an interrupt // When a software HALT instruction is executed, the CPU executes NOPs until an interrupt
@@ -158,14 +159,7 @@ namespace Z80
// received from the memory is ignored and an NOP instruction is forced internally to the // received from the memory is ignored and an NOP instruction is forced internally to the
// CPU.The HALT acknowledge signal is active during this time indicating that the processor // CPU.The HALT acknowledge signal is active during this time indicating that the processor
// is in the HALT state. // is in the HALT state.
_ = this.FetchInitialOpCode(); this.Execute(this.FetchInstruction());
this.Execute(0); // NOP
handled = true;
}
if (!handled)
{
this.Execute(this.FetchInitialOpCode());
} }
} }
@@ -1535,7 +1529,7 @@ namespace Z80
} }
else else
{ {
this.Execute(this.FetchInitialOpCode()); this.Execute(this.FetchInstruction());
} }
break; break;
@@ -1585,15 +1579,15 @@ namespace Z80
break; break;
case 1: // DD prefix case 1: // DD prefix
this._displaced = this._prefixDD = true; this._displaced = this._prefixDD = true;
this.Execute(this.FetchInitialOpCode()); this.Execute(this.FetchInstruction());
break; break;
case 2: // ED prefix case 2: // ED prefix
this._prefixED = true; this._prefixED = true;
this.Execute(this.FetchInitialOpCode()); this.Execute(this.FetchInstruction());
break; break;
case 3: // FD prefix case 3: // FD prefix
this._displaced = this._prefixFD = true; this._displaced = this._prefixFD = true;
this.Execute(this.FetchInitialOpCode()); this.Execute(this.FetchInstruction());
break; break;
default: default:
throw new NotSupportedException("Invalid operation mode"); throw new NotSupportedException("Invalid operation mode");
@@ -1680,10 +1674,10 @@ namespace Z80
// before the RD signal becomes inactive. Clock states T3 and T4 of a fetch cycle are used to // before the RD signal becomes inactive. Clock states T3 and T4 of a fetch cycle are used to
// _refresh dynamic memories. The CPU uses this time to decode and execute the fetched // _refresh dynamic memories. The CPU uses this time to decode and execute the fetched
// instruction so that no other concurrent operation can be performed. // instruction so that no other concurrent operation can be performed.
private byte FetchInitialOpCode() protected override byte FetchInstruction()
{ {
this.LowerM1(); this.LowerM1();
var returned = this.FetchByte(); var returned = base.FetchInstruction();
this.RaiseM1(); this.RaiseM1();
return returned; return returned;
} }