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• 2bd50e5cd2 Fix the single step checker a little master Adrian Conlon 2025-08-25 23:57:52 +01:00
• 17a2b99d6c Remove all cycle accurate processing Adrian Conlon 2025-08-25 23:56:27 +01:00
• 1779d1dc40 Intel processors all seem to act slightly differently with regards to HALT Adrian Conlon 2025-08-17 12:03:51 +01:00
• c67e376d4f Add support for checking deferred EI correctness Adrian Conlon 2025-08-14 14:57:51 +01:00
• 4da07a8fa2 Correct interrupt flag checks in Gameboy checker Adrian Conlon 2025-08-14 11:18:02 +01:00
• a4e704fef4 I give up. This is probably more compatible with Intel derived processors Adrian Conlon 2025-08-13 19:03:25 +01:00
• 7951abde00 Add support for "Gameboy Doctor" log checker. Adrian Conlon 2025-08-13 14:01:14 +01:00
• eb23fbe44c Correction: the least significant bit is *not* zeroed by an IM 2 interrupt Adrian Conlon 2025-08-12 17:19:55 +01:00
• e96a51342a Remove unneeded "using" Adrian Conlon 2025-08-12 08:28:08 +01:00
• 25ca534186 The EI instructions is actually a deferred instruction Adrian Conlon 2025-08-10 21:47:15 +01:00
• d4775cb266 Correct assertion failure during refresh cycle Adrian Conlon 2025-08-10 12:52:48 +01:00
• 558da38f12 Note commonality between Intel-style processors Adrian Conlon 2025-08-10 12:43:34 +01:00
• 2e1573b016 Add support for sub-M-cycle accuracy. Not sure how useful this is! Adrian Conlon 2025-08-10 11:32:53 +01:00
• 072e38f6ee Add a couple of debug assertions Adrian Conlon 2025-08-09 15:10:27 +01:00
• b40224b5af Correct IM 2 indirection Adrian Conlon 2025-08-09 14:52:41 +01:00
• f1febd480e Sort out interrupt timing (I think) Adrian Conlon 2025-08-09 13:29:57 +01:00
• e8a1e7dc6e Sort out Z80/Spectrum pin handling (again!) Adrian Conlon 2025-08-08 21:47:48 +01:00
• 199d0a77b1 Disable interrups as the first act of INT handling Adrian Conlon 2025-08-08 00:03:21 +01:00
• 41be64ad99 Simplfy interrupts on Z80 Adrian Conlon 2025-08-07 19:05:41 +01:00
• d332c57e47 Simplify Z80 port handling Adrian Conlon 2025-08-07 09:56:25 +01:00
• 3a8e379efd Align with Z80 implementation Adrian Conlon 2025-08-07 09:42:52 +01:00
• ed6c7968bd Remove effectively impossible to use methods Adrian Conlon 2025-08-07 09:42:23 +01:00
• 14e4132d34 Small consistency change Adrian Conlon 2025-08-06 16:54:14 +01:00
• 350483fcec Catch another couple of Z80 timing issues Adrian Conlon 2025-08-05 00:14:05 +01:00
• 796042acdf Simplfy intel processor interations Adrian Conlon 2025-08-04 19:47:40 +01:00
• 52ea4b3acd Last trivial Z80 update Adrian Conlon 2025-08-04 18:19:40 +01:00
• 9d208de9bb Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster) Adrian Conlon 2025-08-04 15:47:26 +01:00
• 319190b7a5 More Z80 cycle simplifications and fixes Adrian Conlon 2025-08-03 21:55:24 +01:00
• 6a32d0269d Fix the Z80 checker, so that all cycle actions are checked. Adrian Conlon 2025-08-03 21:54:05 +01:00
• 3ccd9c45ca Adjusted for the latest single-step Z80 tests. Simplify memory update access. Adrian Conlon 2025-08-02 17:49:18 +01:00
• bfc2355337 Correct RRD/RLD timing and XHTL ordering (according to latest Z80 single step tests) Adrian Conlon 2025-08-02 12:26:53 +01:00
• 6143a9d285 Hack to allow single step tests to completely work: disable IO area triggers. Adrian Conlon 2025-08-01 22:59:00 +01:00
• bb63211f17 Fix event names Adrian Conlon 2025-08-01 22:57:38 +01:00
• 60ef099208 Tidy some inconsistencies in various emulation Adrian Conlon 2025-08-01 15:01:20 +01:00
• a252a74d2d Tidy some inconsistencies in z80 emulation Adrian Conlon 2025-08-01 14:59:40 +01:00
• 2f338c6c46 Tidy register increment/decrement a little. Adrian Conlon 2025-07-25 16:32:30 +01:00
• c271b28495 Simplify bus addressing Adrian Conlon 2025-07-05 09:46:59 +01:00
• 3bbf300e05 Simplify switching processor pin handling Adrian Conlon 2025-06-22 21:07:02 +01:00
• 3105930027 Fix BBR/BBS timings in 65C02 Adrian Conlon 2025-06-19 13:27:05 +01:00
• caca3467d9 More unit test stuff. New tests generated by copilot Adrian Conlon 2025-05-13 09:52:12 +01:00
• 12053fd076 Tidy 6809 tests namespace Adrian Conlon 2025-05-12 21:39:42 +01:00
• a5eed89b26 Tidy up all the 6809 stuff Adrian Conlon 2025-05-12 21:08:39 +01:00
• 6e1fc14530 Start tidying up 6809 implementation/testst Adrian Conlon 2025-05-12 19:15:34 +01:00
• adbd16daa2 Get M6809 unit tests running again Adrian Conlon 2025-05-12 12:19:27 +01:00
• e7b025e66e Some speed-up refactoring of the Z80 core Adrian Conlon 2025-05-12 10:17:39 +01:00
• 8331b4818e Couple of small Register16 adjustments Adrian Conlon 2025-05-11 21:30:15 +01:00
• 36e983526e Add increment/decrement operations to the Register16 class Adrian Conlon 2025-05-11 19:24:40 +01:00
• 60d000905f Remove a bunch of analysis warnings Adrian Conlon 2025-05-08 22:03:27 +01:00
• fc2b0470a3 Remove test patterns Adrian Conlon 2025-05-08 22:01:19 +01:00
• 19c18445d6 Remove a couple of pointless "Word"isms Adrian Conlon 2025-05-08 19:46:43 +01:00
• d92926c15b Quite a fun low level rearrangement of the 16-bit register class. Adrian Conlon 2025-05-08 19:46:08 +01:00
• 9e0006187e Port access in Intel processors is 16 rather than 8 bit addressed Adrian Conlon 2025-05-08 13:00:30 +01:00
• eda9519068 Correct some analysis issues Adrian Conlon 2025-05-07 21:30:19 +01:00
• 79c15602eb Small refactor Adrian Conlon 2025-05-07 21:27:01 +01:00
• 293c735ec5 Simplify indirect memory access Adrian Conlon 2025-05-07 11:56:23 +01:00
• 1a09473b5a Read port refactoring Adrian Conlon 2025-05-06 23:05:51 +01:00
• a6051a64ab More IO simplifications Adrian Conlon 2025-05-06 22:51:30 +01:00
• 62f42ef46f Refactored a little, but no functional changes Adrian Conlon 2025-05-06 21:41:32 +01:00
• db1da4f506 Remove extra line Adrian Conlon 2025-05-06 21:39:47 +01:00
• 95783d37aa Reset/power refactoring for z80 Adrian Conlon 2025-05-06 15:37:24 +01:00
• d58095a9d0 Power-on and reset consistency fixes Adrian Conlon 2025-05-06 11:52:33 +01:00
• e1696721f6 Simplifications and refactorings in th intel processors Adrian Conlon 2025-05-05 21:06:39 +01:00
• 37431d08bc Correct LD?R/CP?R block methods. 4 problem instuctions now. Adrian Conlon 2025-05-04 17:47:19 +01:00
• 045907e273 Fix INI/IND flag handling. 8 problems remaining Adrian Conlon 2025-05-04 17:22:23 +01:00
• 6d84c3a41f Get SCF/CCF X/Y flags working correctly. 10 problems reported now. Adrian Conlon 2025-05-04 16:00:08 +01:00
• 93e09c192f Share instruction fetch and halt implementations Adrian Conlon 2025-05-04 11:41:28 +01:00
• 2336222c97 Push more core processor handling into base classes. Adrian Conlon 2025-05-04 10:53:23 +01:00
• 47374e591d With my correct implementation of HALT, I need the fetch to take place during a halted state Adrian Conlon 2025-05-04 08:56:22 +01:00
• e4494e943a PC only proceeds when HALT pin is raised Adrian Conlon 2025-05-04 00:36:01 +01:00
• 853569b2ca Isolate REFRESH pin functionality Adrian Conlon 2025-05-04 00:35:14 +01:00
• cbe871d365 Isolate program counter increment/decrement (to be used for HALT processing) Adrian Conlon 2025-05-03 23:25:06 +01:00
• 2501bdfd28 More block timing issues corrected. 16 issues remaining Adrian Conlon 2025-05-03 22:46:02 +01:00
• 6d8a00876f Fix a bunch of "block" instruction timings. 16 problems remaining. Adrian Conlon 2025-05-03 19:51:36 +01:00
• a0d45eace1 Fix display of registers (from alternate set) when viewing z80 problems Adrian Conlon 2025-05-03 19:18:03 +01:00
• 26457b4a77 Correct timing for 16-bit arithmetic tests. 26 failures remaining Adrian Conlon 2025-05-03 15:03:04 +01:00
• 68328d92fb Fix displaced timing on arithmetic operations for z80. 34 failures now Adrian Conlon 2025-05-03 14:40:38 +01:00
• 506e2b9eda Fix some displaced memory load timing issues. 50 issues remaining. Adrian Conlon 2025-05-03 14:10:18 +01:00
• f9754dd62f Fix some z80 eight-bit load timing issues. 58 issues remaining Adrian Conlon 2025-05-03 13:54:18 +01:00
• 9f2079efae More z80 timing issues fixed. 70 issues remain Adrian Conlon 2025-05-03 13:21:36 +01:00
• 080f203a55 Unify Intel style JR CC code and fix SM83 timing issues. Adrian Conlon 2025-05-03 12:09:34 +01:00
• 0679b95b77 Correct LR35902 HALT test. Whatever problems this has, won't be solved by a hack Adrian Conlon 2025-05-03 11:58:57 +01:00
• 94b8da456b Fix loads of z80 timing issues. 84 timing issues remain. Adrian Conlon 2025-05-03 11:45:55 +01:00
• 898a2bc7ea Try to bring the Z80 fusetest back to life Adrian Conlon 2025-05-03 02:09:31 +01:00
• 946121defb Fix HALT instruction Adrian Conlon 2025-05-03 02:08:52 +01:00
• 561483d65d More timing fixes. 255 timing errors Adrian Conlon 2025-05-03 01:31:44 +01:00
• f4f4357a3e More z80 timing fixes, 261 errors Adrian Conlon 2025-05-03 00:51:20 +01:00
• e1aa220409 Further Z80 timing fixes: 290 failures Adrian Conlon 2025-05-03 00:09:19 +01:00
• 175069d6bf More Z80 timing fixes Adrian Conlon 2025-05-02 20:18:04 +01:00
• 3617608e8c Fix a number of write timing issues Adrian Conlon 2025-05-02 17:46:33 +01:00
• fda52af260 Only DJNZ has the extra tick (presumably to decrement the B register) Adrian Conlon 2025-05-02 14:07:15 +01:00
• 935466ad6f Correct timing issues both conditional and unconditional relative jumpson Z80 Adrian Conlon 2025-05-02 14:03:15 +01:00
• 9670c3fd21 Start correcting timing issues in my Z80 implementation Adrian Conlon 2025-05-02 12:11:54 +01:00
• 07330cc9c8 Move a routine into a slightly better place Adrian Conlon 2025-05-02 10:52:06 +01:00
• 5bae07ff8d Add single stepping Z80 testing code Adrian Conlon 2025-05-02 10:50:49 +01:00
• dd1d141f15 Simplify conditional flag handling in intel processors Adrian Conlon 2025-04-29 12:27:39 +01:00
• 973590690c Fix a bunch of analysis issues Adrian Conlon 2025-04-01 09:32:29 +01:00
• 820fb707b9 Update to latest EightBit library Adrian Conlon 2025-03-29 14:38:36 +00:00
• 1b1b92ac2c More event handling simplification Adrian Conlon 2025-03-29 13:18:54 +00:00
• b461eb97d6 Prefer to use events directly, rather than through "On" methods Adrian Conlon 2025-03-29 11:31:47 +00:00
• 87abbaa75e Tidy IO page access Adrian Conlon 2025-03-28 14:50:53 +00:00