mirror of
https://github.com/MoleskiCoder/EightBitNet.git
synced 2025-11-01 18:16:08 +00:00
305 lines
15 KiB
C#
305 lines
15 KiB
C#
// <copyright file="WDC65C02.cs" company="Adrian Conlon">
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// Copyright (c) Adrian Conlon. All rights reserved.
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// </copyright>
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namespace M6502
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{
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using EightBit;
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public class WDC65C02(Bus bus) : Core(bus)
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{
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private bool _stopped;
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private bool _waiting;
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private bool Stopped
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{
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get => _stopped; set => _stopped = value;
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}
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private bool Waiting
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{
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get => _waiting; set => _waiting = value;
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}
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private bool Paused => Stopped || Waiting;
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#region Interrupts
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protected override void Interrupt(byte vector, InterruptSource source, InterruptType type)
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{
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base.Interrupt(vector, source, type);
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ResetFlag(StatusBits.DF); // Disable decimal mode (Change from MOS6502)
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}
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#endregion
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#region Core instruction dispatching
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protected override bool MaybeExecute()
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{
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if (base.MaybeExecute())
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{
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return true;
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}
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var cycles = Cycles;
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switch (OpCode)
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{
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case 0x02: SwallowFetch(); break; // NOP
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case 0x03: break; // null
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case 0x04: ZeroPageRead(); TSB(); break; // TSB zp
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case 0x07: ZeroPageRead(); RMB(Bit(0)); break; // RMB0 zp
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case 0x0b: break; // null
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case 0x0c: AbsoluteRead(); TSB(); break; // TSB a
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case 0x0f: ZeroPageRead(); BBR(Bit(0)); break; // BBR0 r
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case 0x12: ZeroPageIndirectAddress(); OrR(); break; // ORA (zp),y
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case 0x13: break; // null
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case 0x14: ZeroPageRead(); TRB(); break; // TRB zp
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case 0x17: ZeroPageRead(); RMB(Bit(1)); break; // RMB1 zp
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case 0x1a: SwallowRead(); A = INC(A); break; // INC A
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case 0x1b: break; // null
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case 0x1c: AbsoluteRead(); TRB(); break; // TRB a
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case 0x1f: ZeroPageRead(); BBR(Bit(1)); break; // BBR1 r
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case 0x22: SwallowFetch(); break; // NOP
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case 0x23: break; // null
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case 0x27: ZeroPageRead(); RMB(Bit(2)); break; // RMB2 zp
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case 0x2b: break; // null
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case 0x2f: ZeroPageRead(); BBR(Bit(2)); break; // BBR2 r
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case 0x32: ZeroPageIndirectRead(); AndR(); break; // AND (zp)
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case 0x33: break; // null
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case 0x34: break; // BIT zp,x
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case 0x37: ZeroPageRead(); RMB(Bit(3)); break; // RMB3 zp
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case 0x3a: SwallowRead(); A = DEC(A); break; // DEC A
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case 0x3b: break; // null
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case 0x3c: break; // BIT a,x
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case 0x3f: ZeroPageRead(); BBR(Bit(3)); break; // BBR3 r
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case 0x42: SwallowFetch(); break; // NOP
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case 0x43: break; // null
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case 0x47: ZeroPageRead(); RMB(Bit(4)); break; // RMB4 zp
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case 0x4b: break; // null
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case 0x4f: ZeroPageRead(); BBR(Bit(4)); break; // BBR4 r
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case 0x52: ZeroPageIndirectRead(); EorR(); break; // EOR (zp)
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case 0x53: break; // null
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case 0x57: ZeroPageRead(); RMB(Bit(5)); break; // RMB5 zp
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case 0x5a: SwallowRead(); Push(Y); break; // PHY s
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case 0x5b: break; // null
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case 0x5c: break; // null
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case 0x5f: ZeroPageRead(); BBR(Bit(5)); break; // BBR5 r
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case 0x62: SwallowFetch(); break; // *NOP
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case 0x63: break; // null
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case 0x64: ZeroPageAddress(); MemoryWrite(0); break; // STZ zp
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case 0x67: ZeroPageRead(); RMB(Bit(6)); break; // RMB6 zp
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case 0x6b: break; // null
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case 0x6f: ZeroPageRead(); BBR(Bit(6)); break; // BBR6 r
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case 0x72: ZeroPageIndirectRead(); ADC(); break; // ADC (zp)
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case 0x73: break; // null
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case 0x74: ZeroPageXAddress(); MemoryWrite(0); break; // STZ zp,x
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case 0x77: ZeroPageRead(); RMB(Bit(7)); break; // RMB7 zp
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case 0x7a: SwallowRead(); SwallowPop(); Y = Through(Pop()); break; // PLY s
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case 0x7b: break; // null
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case 0x7c: break; // JMP (a,x)
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case 0x7f: ZeroPageRead(); BBR(Bit(7)); break; // BBR7 r
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case 0x80: Branch(true); break; // BRA r
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case 0x83: break; // null
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case 0x87: ZeroPageRead(); SMB(Bit(0)); break; // SMB0 zp
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case 0x89: break; // BIT # (TBC)
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case 0x8b: break; // null
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case 0x8f: ZeroPageRead(); BBS(Bit(0)); break; // BBS0 r
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case 0x92: ZeroPageIndirectAddress(); MemoryWrite(A); break; // STA (zp)
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case 0x93: break; // null
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case 0x97: ZeroPageRead(); SMB(Bit(1)); break; // SMB1 zp
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case 0x9b: break; // null
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case 0x9c: AbsoluteAddress(); MemoryWrite(0); break; // STZ a
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case 0x9e: AbsoluteXAddress(); MemoryWrite(0); break; // STZ a,x
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case 0x9f: ZeroPageRead(); BBS(Bit(1)); break; // BBS1 r
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case 0xa3: break; // null
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case 0xa7: ZeroPageRead(); SMB(Bit(2)); break; // SMB2 zp
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case 0xab: break; // null
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case 0xaf: ZeroPageRead(); BBS(Bit(2)); break; // BBS2 r
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case 0xb2: ZeroPageIndirectRead(); A = Through(); break; // LDA (zp)
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case 0xb3: break; // null
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case 0xb7: ZeroPageRead(); SMB(Bit(3)); break; // SMB3 zp
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case 0xbb: break; // null
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case 0xbf: ZeroPageRead(); BBS(Bit(3)); break; // BBS3 r
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case 0xc3: break; // null
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case 0xc7: ZeroPageRead(); SMB(Bit(4)); break; // SMB4 zp
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case 0xcb: SwallowRead(); Waiting = true; break; // WAI i
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case 0xcf: ZeroPageRead(); BBS(Bit(4)); break; // BBS4 r
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case 0xd2: ZeroPageIndirectRead(); CMP(A); break; // CMP (zp)
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case 0xd3: break; // null
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case 0xd7: ZeroPageRead(); SMB(Bit(5)); break; // SMB5 zp
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case 0xda: SwallowRead(); Push(X); break; // PHX s
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case 0xdb: SwallowRead(); Stopped = true; break; // STP i
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case 0xdc: SwallowRead(); break; // null
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case 0xdf: ZeroPageRead(); BBS(Bit(5)); break; // BBS5 r
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case 0xe3: break; // null
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case 0xe7: ZeroPageRead(); SMB(Bit(6)); break; // SMB6 zp
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case 0xeb: break; // null
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case 0xef: ZeroPageRead(); BBS(Bit(6)); break; // BBS6 r
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case 0xf2: ZeroPageIndirectRead(); SBC(); break; // SBC (zp)
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case 0xf3: break; // null
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case 0xf7: ZeroPageRead(); SMB(Bit(7)); break; // SMB7 zp
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case 0xfa: SwallowRead(); SwallowPop(); X = Through(Pop()); break; // PLX s
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case 0xfb: break; // null
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case 0xfc: break; // null
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case 0xff: ZeroPageRead(); BBS(Bit(7)); break; // BBS7 r
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}
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return cycles != Cycles;
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}
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public override void PoweredStep()
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{
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if (!Paused)
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{
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base.PoweredStep();
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}
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}
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protected override void OnLoweredRESET()
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{
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base.OnLoweredRESET();
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Stopped = Waiting = false;
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}
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protected override void OnLoweredINT()
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{
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base.OnLoweredINT();
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Waiting = false;
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}
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protected override void OnLoweredNMI()
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{
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base.OnLoweredNMI();
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Waiting = false;
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}
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#endregion
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#region Bus/Memory Access
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protected override void ModifyWrite(byte data)
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{
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// The read will have already taken place...
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MemoryRead(); // Modify cycle (Change from MOS6502)
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MemoryWrite(data); // Write cycle
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}
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#endregion
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#region Addressing modes
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#region Address page fixup
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private readonly Register16 lastFetchAddress = new();
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protected override byte FetchByte()
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{
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lastFetchAddress.Assign(PC);
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return base.FetchByte();
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}
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protected override void Fixup()
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{
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var fixingLow = Bus.Address.Low;
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MemoryRead(lastFetchAddress);
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Bus.Address.Assign(fixingLow, FixedPage);
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}
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protected override void FixupBranch(sbyte relative)
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{
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NoteFixedAddress(PC.Word + relative);
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lastFetchAddress.Assign(Bus.Address); // Effectively negate the use of "lastFetchAddress" for branch fixup usages
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MaybeFixup();
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}
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#endregion
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#region Address resolution
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protected void GetAddress()
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{
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GetWordPaged();
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if (Bus.Address.Low == 0)
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{
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Bus.Address.High++;
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}
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Bus.Address.Assign(Intermediate.Low, MemoryRead());
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}
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protected override void IndirectAddress()
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{
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AbsoluteAddress();
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GetAddress();
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}
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#endregion
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#region Address and read
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private void ZeroPageIndirectRead()
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{
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ZeroPageIndirectAddress();
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MemoryRead();
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}
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#endregion
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#endregion
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private void RMB(byte flag)
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{
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MemoryRead();
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Bus.Data &= (byte)~flag;
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MemoryWrite();
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}
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private void SMB(byte flag)
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{
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MemoryRead();
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Bus.Data |= flag;
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MemoryWrite();
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}
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private void BBS(byte flag)
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{
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MemoryRead();
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Branch(Bus.Data & flag);
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}
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private void BBR(byte flag)
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{
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MemoryRead();
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BranchNot(Bus.Data & flag);
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}
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private void TSB()
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{
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AdjustZero((byte)(A & Bus.Data));
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ModifyWrite((byte)(A | Bus.Data));
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}
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private void TRB()
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{
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AdjustZero((byte)(A & Bus.Data));
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ModifyWrite((byte)(~A & Bus.Data));
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}
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}
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} |