mirror of
https://github.com/MoleskiCoder/EightBitNet.git
synced 2024-11-14 23:05:32 +00:00
826 lines
30 KiB
C#
826 lines
30 KiB
C#
// <copyright file="Disassembler.cs" company="Adrian Conlon">
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// Copyright (c) Adrian Conlon. All rights reserved.
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// </copyright>
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namespace EightBit
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{
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public class Disassembler
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{
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private bool prefixCB = false;
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private bool prefixDD = false;
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private bool prefixED = false;
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private bool prefixFD = false;
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public Disassembler(Bus bus) => this.Bus = bus;
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public Bus Bus { get; }
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public static string AsFlag(byte value, StatusBits flag, string represents) => (value & (byte)flag) != 0 ? represents : "-";
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public static string AsFlags(byte value) =>
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$"{AsFlag(value, StatusBits.SF, "S")}"
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+ $"{AsFlag(value, StatusBits.ZF, "Z")}"
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+ $"{AsFlag(value, StatusBits.YF, "Y")}"
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+ $"{AsFlag(value, StatusBits.HC, "H")}"
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+ $"{AsFlag(value, StatusBits.XF, "X")}"
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+ $"{AsFlag(value, StatusBits.PF, "P")}"
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+ $"{AsFlag(value, StatusBits.NF, "N")}"
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+ $"{AsFlag(value, StatusBits.CF, "C")}";
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public static string State(Z80 cpu)
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{
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var pc = cpu.PC;
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var sp = cpu.SP;
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var a = cpu.A;
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var f = cpu.F;
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var b = cpu.B;
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var c = cpu.C;
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var d = cpu.D;
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var e = cpu.E;
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var h = cpu.H;
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var l = cpu.L;
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var i = cpu.IV;
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var r = cpu.REFRESH;
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var im = cpu.IM;
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return
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$"PC={pc.Word:x4} SP={sp.Word:x4} "
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+ $"A={a:x2} F={AsFlags(f)} "
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+ $"B={b:x2} C={c:x2} "
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+ $"D={d:x2} E={e:x2} "
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+ $"H={h:x2} L={l:x2} "
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+ $"IX={cpu.IX.Word:x4} "
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+ $"IY={cpu.IY.Word:x4} "
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+ $"I={i:x2} R={(byte)r:x2} "
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+ $"IM={im} "
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+ $"IFF1={(cpu.IFF1 ? 1 : 0)} "
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+ $"{(cpu.RESET.Lowered() ? "R" : "-")}"
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+ $"{(cpu.INT.Lowered() ? "I" : "-")}"
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+ $"{(cpu.HALT.Lowered() ? "H" : "-")}"
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+ $"{(cpu.NMI.Lowered() ? "N" : "-")}";
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}
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public string Disassemble(Z80 cpu)
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{
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this.prefixCB = this.prefixDD = this.prefixED = this.prefixFD = false;
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return this.Disassemble(cpu, cpu.PC.Word);
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}
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private static string CC(int flag)
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{
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switch (flag)
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{
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case 0:
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return "NZ";
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case 1:
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return "Z";
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case 2:
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return "NC";
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case 3:
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return "C";
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case 4:
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return "PO";
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case 5:
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return "PE";
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case 6:
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return "P";
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case 7:
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return "M";
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}
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throw new System.ArgumentOutOfRangeException(nameof(flag));
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}
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private static string ALU(int which)
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{
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switch (which)
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{
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case 0: // ADD A,n
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return "ADD";
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case 1: // ADC
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return "ADC";
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case 2: // SUB n
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return "SUB";
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case 3: // SBC A,n
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return "SBC";
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case 4: // AND n
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return "AND";
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case 5: // XOR n
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return "XOR";
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case 6: // OR n
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return "OR";
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case 7: // CP n
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return "CP";
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}
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throw new System.ArgumentOutOfRangeException(nameof(which));
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}
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private string Disassemble(Z80 cpu, ushort pc)
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{
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var opCode = this.Bus.Peek(pc);
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var decoded = cpu.GetDecodedOpCode(opCode);
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var x = decoded.X;
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var y = decoded.Y;
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var z = decoded.Z;
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var p = decoded.P;
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var q = decoded.Q;
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var immediate = this.Bus.Peek((ushort)(pc + 1));
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var absolute = cpu.PeekWord((ushort)(pc + 1)).Word;
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var displacement = (sbyte)immediate;
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var relative = pc + displacement + 2;
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var indexedImmediate = this.Bus.Peek((ushort)(pc + 1));
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var dumpCount = 0;
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var output = $"{opCode:x2}";
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var specification = string.Empty;
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if (this.prefixCB)
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{
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output += this.DisassembleCB(ref specification, x, y, z);
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}
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else if (this.prefixED)
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{
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output += this.DisassembleED(cpu, pc, ref specification, ref dumpCount, x, y, z, p, q);
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}
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else
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{
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output += this.DisassembleOther(cpu, pc, ref specification, ref dumpCount, x, y, z, p, q);
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}
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for (var i = 0; i < dumpCount; ++i)
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{
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output += $"{this.Bus.Peek((ushort)(pc + i + 1)):x2}";
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}
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var outputFormatSpecification = !this.prefixDD;
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if (this.prefixDD)
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{
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if (opCode != 0xdd)
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{
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outputFormatSpecification = true;
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}
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}
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if (outputFormatSpecification)
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{
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output += '\t';
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output += string.Format(specification, (int)immediate, (int)absolute, relative, (int)displacement, indexedImmediate);
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}
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return output;
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}
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private string DisassembleCB(ref string specification, int x, int y, int z)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0: // rot[y] r[z]
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switch (y)
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{
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case 0:
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specification = $"RLC {this.R(z)}";
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break;
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case 1:
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specification = $"RRC {this.R(z)}";
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break;
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case 2:
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specification = $"RL {this.R(z)}";
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break;
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case 3:
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specification = $"RR {this.R(z)}";
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break;
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case 4:
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specification = $"SLA {this.R(z)}";
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break;
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case 5:
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specification = $"SRA {this.R(z)}";
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break;
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case 6:
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specification = $"SWAP {this.R(z)}";
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break;
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case 7:
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specification = $"SRL {this.R(z)}";
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break;
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}
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break;
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case 1: // BIT y, r[z]
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specification = $"BIT {y},{this.R(z)}";
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break;
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case 2: // RES y, r[z]
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specification = $"RES {y},{this.R(z)}";
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break;
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case 3: // SET y, r[z]
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specification = $"SET {y},{this.R(z)}";
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break;
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}
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return output;
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}
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private string DisassembleED(Z80 cpu, ushort pc, ref string specification, ref int dumpCount, int x, int y, int z, int p, int q)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0:
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case 3:
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specification = "NONI NOP";
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break;
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case 1:
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switch (z)
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{
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case 2:
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switch (q)
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{
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case 0: // SBC HL,rp
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specification = $"SBC HL,{this.RP(p)}";
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break;
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case 1: // ADC HL,rp
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specification = $"ADC HL,{this.RP(p)}";
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break;
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}
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break;
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case 3:
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switch (q)
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{
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case 0: // LD (nn),rp
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specification = "LD ({1:X4}H)," + this.RP(p);
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break;
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case 1: // LD rp,(nn)
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specification = "LD " + this.RP(p) + ",(%2$04XH)";
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break;
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}
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dumpCount += 2;
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break;
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case 4: // Negate accumulator
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specification = "NEG";
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break;
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case 5: // Return from interrupt
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switch (y)
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{
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case 1:
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specification = "RETI";
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break;
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default:
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specification = "RETN";
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break;
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}
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break;
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case 6: // Set interrupt mode
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switch (y)
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{
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case 0:
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case 1:
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case 4:
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case 5:
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specification = "IM 0";
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break;
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case 2:
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case 6:
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specification = "IM 1";
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break;
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case 3:
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case 7:
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specification = "IM 2";
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break;
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}
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break;
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case 7:
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switch (y)
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{
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case 0:
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specification = "LD I,A";
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break;
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case 1:
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specification = "LD R,A";
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break;
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case 2:
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specification = "LD A,I";
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break;
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case 3:
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specification = "LD A,R";
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break;
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case 4:
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specification = "RRD";
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break;
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case 5:
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specification = "RLD";
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break;
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case 6:
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case 7:
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specification = "NOP";
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break;
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}
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break;
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}
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break;
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case 2:
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switch (z)
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{
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case 0: // LD
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switch (y)
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{
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case 4: // LDI
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specification = "LDI";
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break;
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case 5: // LDD
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specification = "LDD";
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break;
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case 6: // LDIR
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specification = "LDIR";
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break;
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case 7: // LDDR
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specification = "LDDR";
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break;
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}
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break;
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case 1: // CP
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switch (y)
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{
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case 4: // CPI
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specification = "CPI";
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break;
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case 5: // CPD
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specification = "CPD";
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break;
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case 6: // CPIR
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specification = "CPIR";
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break;
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case 7: // CPDR
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specification = "CPDR";
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break;
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}
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break;
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case 2: // IN
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switch (y)
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{
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case 4: // INI
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specification = "INI";
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break;
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case 5: // IND
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specification = "IND";
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break;
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case 6: // INIR
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specification = "INIR";
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break;
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case 7: // INDR
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specification = "INDR";
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break;
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}
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break;
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case 3: // OUT
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switch (y)
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{
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case 4: // OUTI
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specification = "OUTI";
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break;
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case 5: // OUTD
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specification = "OUTD";
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break;
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case 6: // OTIR
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specification = "OTIR";
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break;
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case 7: // OTDR
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specification = "OTDR";
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break;
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}
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break;
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}
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break;
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}
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return output;
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}
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private string DisassembleOther(Z80 cpu, ushort pc, ref string specification, ref int dumpCount, int x, int y, int z, int p, int q)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0:
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switch (z)
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{
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case 0: // Relative jumps and assorted ops
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switch (y)
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{
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case 0: // NOP
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specification = "NOP";
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break;
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case 1: // EX AF AF'
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specification = "EX AF AF'";
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break;
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case 2: // DJNZ d
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specification = "DJNZ {2:X4}H";
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dumpCount += 2;
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break;
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case 3: // JR d
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specification = "JR {2:X4}H";
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dumpCount++;
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break;
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default: // JR cc,d
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specification = "JR " + CC(y - 4) + ",{2:X4}H";
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dumpCount++;
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q)
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{
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case 0: // LD rp,nn
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specification = "LD " + this.RP(p) + ",{1:X4}H";
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dumpCount += 2;
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break;
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case 1: // ADD HL,rp
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specification = $"ADD HL,{this.RP(p)}";
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q)
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{
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case 0:
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switch (p)
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{
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case 0: // LD (BC),A
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specification = "LD (BC),A";
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break;
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case 1: // LD (DE),A
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specification = "LD (DE),A";
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break;
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case 2: // LD (nn),HL
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specification = "LD ({1:X4}H),HL";
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dumpCount += 2;
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break;
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case 3: // LD (nn),A
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specification = "LD ({1:X4}H),A";
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dumpCount += 2;
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break;
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}
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break;
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case 1:
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switch (p)
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{
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case 0: // LD A,(BC)
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specification = "LD A,(BC)";
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break;
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case 1: // LD A,(DE)
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specification = "LD A,(DE)";
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break;
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case 2: // LD HL,(nn)
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specification = "LD HL,({1:X4}H)";
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dumpCount += 2;
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break;
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case 3: // LD A,(nn)
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specification = "LD A,({1:X4}H)";
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dumpCount += 2;
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break;
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}
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break;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q)
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{
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case 0: // INC rp
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specification = $"INC {this.RP(p)}";
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break;
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case 1: // DEC rp
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specification = $"DEC {this.RP(p)}";
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break;
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}
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break;
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case 4: // 8-bit INC
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specification = $"INC {this.R(y)}";
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break;
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case 5: // 8-bit DEC
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specification = $"DEC {this.R(y)}";
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break;
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case 6: // 8-bit load immediate
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specification = $"LD {this.R(y)}";
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if (y == 6 && (this.prefixDD || this.prefixFD))
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{
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specification += ",{4:X2}H";
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dumpCount++;
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}
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else
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{
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specification += ",{0:X2}H";
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}
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dumpCount++;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y)
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{
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case 0:
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specification = "RLCA";
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break;
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case 1:
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specification = "RRCA";
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break;
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case 2:
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specification = "RLA";
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break;
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case 3:
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specification = "RRA";
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break;
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case 4:
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specification = "DAA";
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break;
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case 5:
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specification = "CPL";
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break;
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case 6:
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specification = "SCF";
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break;
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case 7:
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specification = "CCF";
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break;
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}
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break;
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}
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break;
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case 1: // 8-bit loading
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if (z == 6 && y == 6)
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{
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specification = "HALT"; // Exception (replaces LD (HL), (HL))
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}
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else
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{
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specification = $"LD {this.R(y)},{this.R(z)}";
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}
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break;
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case 2: // Operate on accumulator and register/memory location
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specification = $"{ALU(y)} A,{this.R(z)}";
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break;
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case 3:
|
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switch (z)
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{
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case 0: // Conditional return
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specification = $"RET {CC(y)}";
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break;
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case 1: // POP & various ops
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switch (q)
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{
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case 0: // POP rp2[p]
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specification = $"POP {this.RP2(p)}";
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break;
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case 1:
|
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switch (p)
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{
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case 0: // RET
|
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specification = "RET";
|
|
break;
|
|
case 1: // EXX
|
|
specification = "EXX";
|
|
break;
|
|
case 2: // JP (HL)
|
|
specification = "JP (HL)";
|
|
break;
|
|
case 3: // LD SP,HL
|
|
specification = "LD SP,HL";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 2: // Conditional jump
|
|
specification = $"JP {CC(y)}" + ",{1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 3: // Assorted operations
|
|
switch (y)
|
|
{
|
|
case 0: // JP nn
|
|
specification = "JP {1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 1: // CB prefix
|
|
this.prefixCB = true;
|
|
output += this.Disassemble(cpu, ++pc);
|
|
break;
|
|
case 2: // OUT (n),A
|
|
specification = "OUT ({0:X2}H),A";
|
|
dumpCount++;
|
|
break;
|
|
case 3: // IN A,(n)
|
|
specification = "IN A,({0:X2}H)";
|
|
dumpCount++;
|
|
break;
|
|
case 4: // EX (SP),HL
|
|
specification = "EX (SP),HL";
|
|
break;
|
|
case 5: // EX DE,HL
|
|
specification = "EX DE,HL";
|
|
break;
|
|
case 6: // DI
|
|
specification = "DI";
|
|
break;
|
|
case 7: // EI
|
|
specification = "EI";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 4: // Conditional call: CALL cc[y], nn
|
|
specification = $"CALL {CC(y)}" + ",{1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 5: // PUSH & various ops
|
|
switch (q)
|
|
{
|
|
case 0: // PUSH rp2[p]
|
|
specification = $"PUSH {this.RP2(p)}";
|
|
break;
|
|
case 1:
|
|
switch (p)
|
|
{
|
|
case 0: // CALL nn
|
|
specification = "CALL {1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 1: // DD prefix
|
|
this.prefixDD = true;
|
|
output += this.Disassemble(cpu, ++pc);
|
|
break;
|
|
case 2: // ED prefix
|
|
this.prefixED = true;
|
|
output += this.Disassemble(cpu, ++pc);
|
|
break;
|
|
case 3: // FD prefix
|
|
this.prefixFD = true;
|
|
output += this.Disassemble(cpu, ++pc);
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
specification = ALU(y) + " A,{0:X2}H";
|
|
dumpCount++;
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
specification = $"RST {y * 8:X2}";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
return output;
|
|
}
|
|
|
|
private string RP(int rp)
|
|
{
|
|
switch (rp)
|
|
{
|
|
case 0:
|
|
return "BC";
|
|
case 1:
|
|
return "DE";
|
|
case 2:
|
|
if (this.prefixDD)
|
|
{
|
|
return "IX";
|
|
}
|
|
|
|
if (this.prefixFD)
|
|
{
|
|
return "IY";
|
|
}
|
|
|
|
return "HL";
|
|
case 3:
|
|
return "SP";
|
|
}
|
|
|
|
throw new System.ArgumentOutOfRangeException(nameof(rp));
|
|
}
|
|
|
|
private string RP2(int rp)
|
|
{
|
|
switch (rp)
|
|
{
|
|
case 0:
|
|
return "BC";
|
|
case 1:
|
|
return "DE";
|
|
case 2:
|
|
if (this.prefixDD)
|
|
{
|
|
return "IX";
|
|
}
|
|
|
|
if (this.prefixFD)
|
|
{
|
|
return "IY";
|
|
}
|
|
|
|
return "HL";
|
|
case 3:
|
|
return "AF";
|
|
}
|
|
|
|
throw new System.ArgumentOutOfRangeException(nameof(rp));
|
|
}
|
|
|
|
private string R(int r)
|
|
{
|
|
switch (r)
|
|
{
|
|
case 0:
|
|
return "B";
|
|
case 1:
|
|
return "C";
|
|
case 2:
|
|
return "D";
|
|
case 3:
|
|
return "E";
|
|
case 4:
|
|
if (this.prefixDD)
|
|
{
|
|
return "IXH";
|
|
}
|
|
|
|
if (this.prefixFD)
|
|
{
|
|
return "IYH";
|
|
}
|
|
|
|
return "H";
|
|
case 5:
|
|
if (this.prefixDD)
|
|
{
|
|
return "IXL";
|
|
}
|
|
|
|
if (this.prefixFD)
|
|
{
|
|
return "IYL";
|
|
}
|
|
|
|
return "L";
|
|
case 6:
|
|
if (this.prefixDD || this.prefixFD)
|
|
{
|
|
if (this.prefixDD)
|
|
{
|
|
return "IX+{4}";
|
|
}
|
|
|
|
if (this.prefixFD)
|
|
{
|
|
return "IY+{4}";
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return "(HL)";
|
|
}
|
|
|
|
break;
|
|
case 7:
|
|
return "A";
|
|
}
|
|
|
|
throw new System.ArgumentOutOfRangeException(nameof(r));
|
|
}
|
|
}
|
|
}
|