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Fix order of remainder results from div32

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David Schmenk
2024-07-07 16:43:10 -07:00
parent a63fed59c9
commit 3a488a5854
1 changed files with 24 additions and 24 deletions
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48
src/libsrc/int32.pla
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@@ -342,10 +342,10 @@ export asm divi16(imm16)#2
_DIV STY DVSIGN ; LSB = SIGN OF DVSR _DIV STY DVSIGN ; LSB = SIGN OF DVSR
DEX ; REMNDR = ESTK..ESTK+1 DEX ; REMNDR = ESTK..ESTK+1
LDY #$00 LDY #$00
STY ESTKL+0,X
STY ESTKH+0,X
STY ESTKL+1,X STY ESTKL+1,X
STY ESTKH+1,X STY ESTKH+1,X
STY ESTKL+0,X
STY ESTKH+0,X
LDA SRC+0 ; DIVIDE BY 0? LDA SRC+0 ; DIVIDE BY 0?
ORA SRC+1 ORA SRC+1
ORA SRC+2 ORA SRC+2
@@ -387,29 +387,29 @@ _DIV STY DVSIGN ; LSB = SIGN OF DVSR
ROL ACCUM32+3 ROL ACCUM32+3
DEY DEY
BCC - BCC -
- ROL ESTKL+0,X ; REMNDR - ROL ESTKL+1,X ; REMNDR
ROL ESTKH+0,X
ROL ESTKL+1,X
ROL ESTKH+1,X ROL ESTKH+1,X
LDA ESTKL+0,X ; REMNDR ROL ESTKL+0,X
ROL ESTKH+0,X
LDA ESTKL+1,X ; REMNDR
CMP SRC+0 ; DVSR CMP SRC+0 ; DVSR
LDA ESTKH+0,X ; COMPARE LDA ESTKH+1,X ; COMPARE
SBC SRC+1 SBC SRC+1
LDA ESTKL+1,X LDA ESTKL+0,X
SBC SRC+2 SBC SRC+2
LDA ESTKH+1,X LDA ESTKH+0,X
SBC SRC+3 SBC SRC+3
BCC + ; IS LESS THAN? BCC + ; IS LESS THAN?
STA ESTKH+1,X
LDA ESTKL+0,X ; REMNDR
SBC SRC+0 ; DVSR
STA ESTKL+0,X ; SUBTRACT
LDA ESTKH+0,X
SBC SRC+1
STA ESTKH+0,X STA ESTKH+0,X
LDA ESTKL+1,X LDA ESTKL+1,X ; REMNDR
SBC SRC+0 ; DVSR
STA ESTKL+1,X ; SUBTRACT
LDA ESTKH+1,X
SBC SRC+1
STA ESTKH+1,X
LDA ESTKL+0,X
SBC SRC+2 SBC SRC+2
STA ESTKL+1,X STA ESTKL+0,X
SEC SEC
+ ROL ACCUM32+0 ; DVDND + ROL ACCUM32+0 ; DVDND
ROL ACCUM32+1 ; ROTATE IN RESULT ROL ACCUM32+1 ; ROTATE IN RESULT
@@ -421,17 +421,17 @@ _DIV STY DVSIGN ; LSB = SIGN OF DVSR
BPL + BPL +
TYA TYA
SEC SEC
SBC ESTKL+0,X
STA ESTKL+0,X
TYA
SBC ESTKH+0,X
STA ESTKH+0,X
TYA
SBC ESTKL+1,X SBC ESTKL+1,X
STA ESTKL+1,X STA ESTKL+1,X
TYA TYA
SBC ESTKH+1,X SBC ESTKH+1,X
STA ESTKH+1,X STA ESTKH+1,X
TYA
SBC ESTKL+0,X
STA ESTKL+0,X
TYA
SBC ESTKH+0,X
STA ESTKH+0,X
LDA DVSIGN LDA DVSIGN
+ LSR + LSR
BCC + BCC +
@@ -663,7 +663,7 @@ export def i32tos(i32ptr, strptr)#1
putc('-') putc('-')
fin fin
repeat repeat
drop, rem = divi16(10) // Only care about LSW of remainder rem, drop = divi16(10) // Only care about LSW of remainder
^iptr = rem + '0' ^iptr = rem + '0'
iptr-- iptr--
until iseqi16(0) until iseqi16(0)