From 07541d791334ec7d85ace98ba12fe70d1254c534 Mon Sep 17 00:00:00 2001
From: Chris Pressey <cpressey@catseye.tc>
Date: Wed, 25 Apr 2018 13:15:53 +0100
Subject: [PATCH] Compile code for saving a, x, or y on the stack.

---
 src/sixtypical/compiler.py      | 26 +++++++++++++++++++++++++-
 src/sixtypical/gen6502.py       | 12 ++++++++++++
 tests/SixtyPical Compilation.md | 24 ++++++++++++++++++++++++
 3 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/src/sixtypical/compiler.py b/src/sixtypical/compiler.py
index a7d0f64..aa0efc7 100644
--- a/src/sixtypical/compiler.py
+++ b/src/sixtypical/compiler.py
@@ -1,6 +1,6 @@
 # encoding: UTF-8
 
-from sixtypical.ast import Program, Routine, Block, Instr, SingleOp, If, Repeat, For, WithInterruptsOff
+from sixtypical.ast import Program, Routine, Block, Instr, SingleOp, If, Repeat, For, WithInterruptsOff, Save
 from sixtypical.model import (
     ConstantRef, LocationRef, IndexedRef, IndirectRef, AddressRef,
     TYPE_BIT, TYPE_BYTE, TYPE_WORD,
@@ -12,6 +12,7 @@ from sixtypical.gen6502 import (
     Immediate, Absolute, AbsoluteX, AbsoluteY, ZeroPage, Indirect, IndirectY, Relative,
     LDA, LDX, LDY, STA, STX, STY,
     TAX, TAY, TXA, TYA,
+    PHA, PLA,
     CLC, SEC, ADC, SBC, ROL, ROR,
     INC, INX, INY, DEC, DEX, DEY,
     CMP, CPX, CPY, AND, ORA, EOR,
@@ -169,6 +170,8 @@ class Compiler(object):
             return self.compile_for(instr)
         elif isinstance(instr, WithInterruptsOff):
             return self.compile_with_interrupts_off(instr)
+        elif isinstance(instr, Save):
+            return self.compile_save(instr)
         else:
             raise NotImplementedError
 
@@ -613,3 +616,24 @@ class Compiler(object):
         self.emitter.emit(SEI())
         self.compile_block(instr.block)
         self.emitter.emit(CLI())
+
+    def compile_save(self, instr):
+        location = instr.locations[0]
+        if location == REG_A:
+            self.emitter.emit(PHA())
+            self.compile_block(instr.block)
+            self.emitter.emit(PLA())
+        elif location == REG_X:
+            self.emitter.emit(TXA())
+            self.emitter.emit(PHA())
+            self.compile_block(instr.block)
+            self.emitter.emit(PLA())
+            self.emitter.emit(TAX())
+        elif location == REG_Y:
+            self.emitter.emit(TYA())
+            self.emitter.emit(PHA())
+            self.compile_block(instr.block)
+            self.emitter.emit(PLA())
+            self.emitter.emit(TAY())
+        else:
+            raise NotImplementedError
diff --git a/src/sixtypical/gen6502.py b/src/sixtypical/gen6502.py
index c3c91d9..7b8d07c 100644
--- a/src/sixtypical/gen6502.py
+++ b/src/sixtypical/gen6502.py
@@ -306,6 +306,18 @@ class ORA(Instruction):
     }
 
 
+class PHA(Instruction):
+    opcodes = {
+        Implied:   0x48,
+    }
+
+
+class PLA(Instruction):
+    opcodes = {
+        Implied:   0x68,
+    }
+
+
 class ROL(Instruction):
     opcodes = {
         Implied:   0x2a,    # Accumulator
diff --git a/tests/SixtyPical Compilation.md b/tests/SixtyPical Compilation.md
index fb45bc0..f08d835 100644
--- a/tests/SixtyPical Compilation.md	
+++ b/tests/SixtyPical Compilation.md	
@@ -579,6 +579,30 @@ Compiling `for ... down to`.
     = $0815   BNE $080F
     = $0817   RTS
 
+Compiling `save`.
+
+    | routine main
+    |   inputs a
+    |   outputs a
+    |   trashes z, n
+    | {
+    |     save a {
+    |         save x {
+    |             ld a, 0
+    |             ld x, 1
+    |         }
+    |     }
+    | }
+    = $080D   PHA
+    = $080E   TXA
+    = $080F   PHA
+    = $0810   LDA #$00
+    = $0812   LDX #$01
+    = $0814   PLA
+    = $0815   TAX
+    = $0816   PLA
+    = $0817   RTS
+
 Indexed access.
 
     | byte one