mirror of
https://github.com/forth-ev/VolksForth.git
synced 2024-07-09 14:29:01 +00:00
579 lines
37 KiB
Plaintext
579 lines
37 KiB
Plaintext
Screen 0 not modified
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0 \ 8086 Assembler cas 10nov05
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1
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2 The 8086 Assembler was written by Mike Perry.
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3 To create and assembler language definition, use the defining
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4 word CODE. It must be terminated with either END-CODE or
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5 its synonym C;. How the assembler operates is a very
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6 interesting example of the power of CREATE DOES> Basically
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7 the instructions are categorized and a defining word is
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8 created for each category. When the nmemonic for the
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9 instruction is interpreted, it compiles itself.
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10
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11 Adapted for volksFORTH by Klaus Schleisiek
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12
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13 No really tested, but
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14 CODE TEST TOS PUSH 1 # TOS MOV NEXT END-CODE
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15 works!
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Screen 1 not modified
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0 \ 8086 Assembler ks cas 10nov05
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1 Onlyforth
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2 Vocabulary Assembler
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3 : octal 8 Base ! ;
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4
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5 decimal 1 14 +THRU clear
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6
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7 Onlyforth
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8
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9 : Code Create [ Assembler ] here dup 2- ! Assembler ;
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10
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11 CR .( 8086 Assembler loaded )
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12 Onlyforth
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13
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14
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15
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Screen 2 not modified
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0 \ 8086 Assembler ks 19 m<>r 88
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1 : LABEL CREATE ASSEMBLER ;
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2 \ 232 CONSTANT DOES-OP
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3 \ 3 CONSTANT DOES-SIZE
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4 \ : DOES? ( IP -- IP' F )
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5 \ DUP DOES-SIZE + SWAP C@ DOES-OP = ;
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6 ASSEMBLER ALSO DEFINITIONS
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7 : C; ( -- ) END-CODE ;
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8 OCTAL
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9 DEFER C, FORTH ' C, ASSEMBLER IS C,
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10 DEFER , FORTH ' , ASSEMBLER IS ,
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11 DEFER HERE FORTH ' HERE ASSEMBLER IS HERE
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12 DEFER ?>MARK
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13 DEFER ?>RESOLVE
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14 DEFER ?<MARK
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15 DEFER ?<RESOLVE
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Screen 3 not modified
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0 \ 8086 Assembler Register Definitions ks 19 m<>r 88
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1 | : REG 11 * SWAP 1000 * OR CONSTANT ;
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2 | : REGS ( MODE N -- ) SWAP 0 DO DUP I REG LOOP DROP ;
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3
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4 10 0 REGS AL CL DL BL AH CH DH BH
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5 10 1 REGS AX CX DX BX SP BP SI DI
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6 10 2 REGS [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] [BP] [BX]
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7 4 2 REGS [SI+BX] [DI+BX] [SI+BP] [DI+BP]
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8 4 3 REGS ES CS SS DS
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9 3 4 REGS # #) S#)
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10
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11 BP Constant UP [BP] Constant [UP] \ User Pointer
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12 SI CONSTANT IP [SI] CONSTANT [IP] ( INTERPRETER POINTER )
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13 DI Constant W [DI] Constant [W] \ WORKING REGISTER
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14 BX Constant RP [BX] Constant [RP] \ Return Stack Pointer
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15 DX Constant TOS \ Top Of Stack im Register
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Screen 4 not modified
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0 \ Addressing Modes ks 19 m<>r 88
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1 | : MD CREATE 1000 * , DOES> @ SWAP 7000 AND = 0<> ;
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2 | 0 MD R8? | 1 MD R16? | 2 MD MEM? | 3 MD SEG? | 4 MD #?
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3 | : REG? ( n -- f ) 7000 AND 2000 < 0<> ;
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4 | : BIG? ( N -- F ) ABS -200 AND 0<> ;
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5 | : RLOW ( n1 -- n2 ) 7 AND ;
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6 | : RMID ( n1 -- n2 ) 70 AND ;
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7 | VARIABLE SIZE SIZE ON
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8 : BYTE ( -- ) SIZE OFF ;
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9 | : OP, ( N OP -- ) OR C, ;
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10 | : W, ( OP MR -- ) R16? 1 AND OP, ;
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11 | : SIZE, ( OP -- OP' ) SIZE @ 1 AND OP, ;
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12 | : ,/C, ( n f -- ) IF , ELSE C, THEN ;
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13 | : RR, ( MR1 MR2 -- ) RMID SWAP RLOW OR 300 OP, ;
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14 | VARIABLE LOGICAL
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15 | : B/L? ( n -- f ) BIG? LOGICAL @ OR ;
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Screen 5 not modified
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0 \ Addressing ks 19 m<>r 88
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1 | : MEM, ( DISP MR RMID -- ) OVER #) =
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2 IF RMID 6 OP, DROP ,
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3 ELSE RMID OVER RLOW OR -ROT [BP] = OVER 0= AND
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4 IF SWAP 100 OP, C, ELSE SWAP OVER BIG?
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5 IF 200 OP, , ELSE OVER 0=
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6 IF C, DROP ELSE 100 OP, C,
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7 THEN THEN THEN THEN ;
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8 | : WMEM, ( DISP MEM REG OP -- ) OVER W, MEM, ;
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9 | : R/M, ( MR REG -- )
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10 OVER REG? IF RR, ELSE MEM, THEN ;
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11 | : WR/SM, ( R/M R OP -- ) 2 PICK DUP REG?
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12 IF W, RR, ELSE DROP SIZE, MEM, THEN SIZE ON ;
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13 | VARIABLE INTER
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14 : FAR ( -- ) INTER ON ;
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15 | : ?FAR ( n1 -- n2 ) INTER @ IF 10 OR THEN INTER OFF ;
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Screen 6 not modified
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0 \ Defining Words to Generate Op Codes ks 19 m<>r 88
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1 | : 1MI CREATE C, DOES> C@ C, ;
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2 | : 2MI CREATE C, DOES> C@ C, 12 C, ;
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3 | : 3MI CREATE C, DOES> C@ C, HERE - 1-
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4 DUP -200 177 uWITHIN NOT ABORT" Branch out of Range" C, ;
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5 | : 4MI CREATE C, DOES> C@ C, MEM, ;
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6 | : 5MI CREATE C, DOES> C@ SIZE, SIZE ON ;
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7 | : 6MI CREATE C, DOES> C@ SWAP W, ;
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8 | : 7MI CREATE C, DOES> C@ 366 WR/SM, ;
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9 | : 8MI CREATE C, DOES> C@ SWAP R16? 1 AND OR SWAP # =
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10 IF C, C, ELSE 10 OR C, THEN ;
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11 | : 9MI CREATE C, DOES> C@ OVER R16?
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12 IF 100 OR SWAP RLOW OP, ELSE 376 WR/SM, THEN ;
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13 | : 10MI CREATE C, DOES> C@ OVER CL =
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14 IF NIP 322 ELSE 320 THEN WR/SM, ;
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15
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Screen 7 not modified
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0 \ Defining Words to Generate Op Codes ks 19 m<>r 88
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1 | : 11MI CREATE C, C, DOES> OVER #) =
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2 IF NIP C@ INTER @
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3 IF 1 AND IF 352 ELSE 232 THEN C, SWAP , , INTER OFF
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4 ELSE SWAP HERE - 2- SWAP 2DUP 1 AND SWAP BIG? NOT AND
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5 IF 2 OP, C, ELSE C, 1- , THEN THEN
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6 ELSE OVER S#) = IF NIP #) SWAP THEN
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7 377 C, 1+ C@ ?FAR R/M, THEN ;
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8 | : 12MI CREATE C, C, C, DOES> OVER REG?
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9 IF C@ SWAP RLOW OP, ELSE 1+ OVER SEG?
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10 IF C@ RLOW SWAP RMID OP,
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11 ELSE COUNT SWAP C@ C, MEM,
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12 THEN THEN ;
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13 | : 14MI CREATE C, DOES> C@
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14 DUP ?FAR C, 1 AND 0= IF , THEN ;
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15
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Screen 8 not modified
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0 \ Defining Words to Generate Op Codes ks 19 m<>r 88
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1 | : 13MI CREATE C, C, DOES> COUNT >R C@ LOGICAL ! DUP REG?
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2 IF OVER REG?
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3 IF R> OVER W, SWAP RR, ELSE OVER DUP MEM? SWAP #) = OR
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4 IF R> 2 OR WMEM, ELSE ( # ) NIP DUP RLOW 0= ( ACC? )
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5 IF R> 4 OR OVER W, R16? ,/C,
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6 ELSE OVER B/L? OVER R16? 2DUP AND
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7 -ROT 1 AND SWAP NOT 2 AND OR 200 OP,
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8 SWAP RLOW 300 OR R> OP, ,/C,
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9 THEN THEN THEN
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10 ELSE ( MEM ) ROT DUP REG?
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11 IF R> WMEM,
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12 ELSE ( # ) DROP 2 PICK B/L? DUP NOT 2 AND 200 OR SIZE,
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13 -ROT R> MEM, SIZE @ AND ,/C, SIZE ON
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14 THEN THEN ;
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15
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Screen 9 not modified
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0 \ Instructions ks 19 m<>r 88
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1 : TEST ( source dest -- ) DUP REG?
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2 IF OVER REG?
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3 IF 204 OVER W, SWAP RR, ELSE OVER DUP MEM? SWAP #) = OR
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4 IF 204 WMEM, ELSE ( # ) NIP DUP RLOW 0= ( ACC? )
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5 IF 250 OVER W,
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6 ELSE 366 OVER W, DUP RLOW 300 OP,
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7 THEN R16? ,/C, THEN THEN
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8 ELSE ( MEM ) ROT DUP REG?
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9 IF 204 WMEM,
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10 ELSE ( # ) DROP 366 SIZE, 0 MEM, SIZE @ ,/C, SIZE ON
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11 THEN THEN ;
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12
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13
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14
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15
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Screen 10 not modified
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0 \ Instructions ks 19 m<>r 88
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1 HEX
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2 : ESC ( source ext-opcode -- ) RLOW 0D8 OP, R/M, ;
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3 : INT ( N -- ) 0CD C, C, ;
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4 : SEG ( SEG -- ) RMID 26 OP, ;
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5 : XCHG ( MR1 MR2 -- ) DUP REG?
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6 IF DUP AX =
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7 IF DROP RLOW 90 OP, ELSE OVER AX =
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8 IF NIP RLOW 90 OP, ELSE 86 WR/SM, THEN THEN
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9 ELSE ROT 86 WR/SM, THEN ;
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10
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11 : CS: CS SEG ;
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12 : DS: DS SEG ;
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13 : ES: ES SEG ;
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14 : SS: SS SEG ;
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15
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Screen 11 not modified
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0 \ Instructions ks 19 m<>r 88
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1 : MOV ( S D -- ) DUP SEG?
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2 IF 8E C, R/M, ELSE DUP REG?
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3 IF OVER #) = OVER RLOW 0= AND
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4 IF A0 SWAP W, DROP , ELSE OVER SEG?
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5 IF SWAP 8C C, RR, ELSE OVER # =
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6 IF NIP DUP R16? SWAP RLOW OVER 8 AND OR B0 OP, ,/C,
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7 ELSE 8A OVER W, R/M, THEN THEN THEN
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8 ELSE ( MEM ) ROT DUP SEG?
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9 IF 8C C, MEM, ELSE DUP # =
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10 IF DROP C6 SIZE, 0 MEM, SIZE @ ,/C,
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11 ELSE OVER #) = OVER RLOW 0= AND
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12 IF A2 SWAP W, DROP , ELSE 88 OVER W, R/M,
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13 THEN THEN THEN THEN THEN SIZE ON ;
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14
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15
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Screen 12 not modified
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0 \ Instructions 12Oct83map
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1 37 1MI AAA D5 2MI AAD D4 2MI AAM 3F 1MI AAS
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2 0 10 13MI ADC 0 00 13MI ADD 2 20 13MI AND 10 E8 11MI CALL
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3 98 1MI CBW F8 1MI CLC FC 1MI CLD FA 1MI CLI
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4 F5 1MI CMC 0 38 13MI CMP A6 5MI CMPS 99 1MI CWD
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5 27 1MI DAA 2F 1MI DAS 08 9MI DEC 30 7MI DIV
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6 ( ESC ) F4 1MI HLT 38 7MI IDIV 28 7MI IMUL
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7 E4 8MI IN 00 9MI INC ( INT ) 0CE 1MI INTO
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8 0CF 1MI IRET 77 3MI JA 73 3MI JAE 72 3MI JB
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9 76 3MI JBE E3 3MI JCXZ 74 3MI JE 7F 3MI JG
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10 7D 3MI JGE 7C 3MI JL 7E 3MI JLE 20 E9 11MI JMP
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11 75 3MI JNE 71 3MI JNO 79 3MI JNS 70 3MI JO
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12 7A 3MI JPE 7B 3MI JPO 78 3MI JS 9F 1MI LAHF
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13 C5 4MI LDS 8D 4MI LEA C4 4MI LES F0 1MI LOCK
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14 0AC 6MI LODS E2 3MI LOOP E1 3MI LOOPE E0 3MI LOOPNE
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15
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Screen 13 not modified
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0 \ Instructions 12Apr84map
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1 ( MOV ) 0A4 5MI MOVS 20 7MI MUL 18 7MI NEG
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2 90 1MI NOP 10 7MI NOT 2 08 13MI OR E6 8MI OUT
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3 8F 07 58 12MI POP 9D 1MI POPF
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4 0FF 36 50 12MI PUSH 9C 1MI PUSHF
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5 10 10MI RCL 18 10MI RCR
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6 F2 1MI REP F2 1MI REPNZ F3 1MI REPZ
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7 C3 14MI RET 00 10MI ROL 8 10MI ROR 9E 1MI SAHF
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8 38 10MI SAR 0 18 13MI SBB 0AE 5MI SCAS ( SEG )
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9 20 10MI SHL 28 10MI SHR F9 1MI STC FD 1MI STD
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10 FB 1MI STI 0AA 6MI STOS 0 28 13MI SUB ( TEST )
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11 9B 1MI WAIT ( XCHG ) D7 1MI XLAT 2 30 13MI XOR
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12 C2 14MI +RET
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13
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14
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15
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Screen 14 not modified
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0 \ Structured Conditionals ks 19 m<>r 88
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1 : A?>MARK ( -- f addr ) TRUE HERE 0 C, ;
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2 : A?>RESOLVE ( f addr -- ) HERE OVER 1+ - SWAP C! true ?pairs ;
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3 : A?<MARK ( -- f addr ) TRUE HERE ;
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4 : A?<RESOLVE ( f addr -- ) HERE 1+ - C, true ?pairs ;
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5 ' A?>MARK ASSEMBLER IS ?>MARK
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6 ' A?>RESOLVE ASSEMBLER IS ?>RESOLVE
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7 ' A?<MARK ASSEMBLER IS ?<MARK
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8 ' A?<RESOLVE ASSEMBLER IS ?<RESOLVE
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9 HEX
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10 75 CONSTANT 0= 74 CONSTANT 0<> 79 CONSTANT 0<
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11 78 CONSTANT 0>= 7D CONSTANT < 7C CONSTANT >=
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12 7F CONSTANT <= 7E CONSTANT > 73 CONSTANT U<
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13 72 CONSTANT U>= 77 CONSTANT U<= 76 CONSTANT U>
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14 71 CONSTANT OV
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15 DECIMAL
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Screen 15 not modified
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0 \ Structured Conditionals cas 10nov05
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1 HEX
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2 : IF C, ?>MARK ;
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3 : THEN ?>RESOLVE ;
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4 : ELSE 0EB IF 2SWAP THEN ;
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5 : BEGIN ?<MARK ;
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6 : UNTIL C, ?<RESOLVE ;
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7 : AGAIN 0EB UNTIL ;
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8 : WHILE IF ;
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9 : REPEAT 2SWAP AGAIN THEN ;
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10 : DO # CX MOV HERE ;
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11 : Next AX lods AX DI xchg 0 [DI] jmp
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12 [ Assembler ] here next-link @ , next-link ! ;
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13 \ volksFORTH uses "inline" Next and a linked list, to find all
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14 \ existing NEXT for the debugger.
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15 DECIMAL
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Screen 16 not modified
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0
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Screen 17 not modified
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0 \ 8086 Assembler 08OCT83HHL
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1 LABEL marks the start of a subroutine whose name returns its
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2 address.
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3 DOES-OP Is the op code of the call instruction used for DOES> U
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4 C; A synonym for END-CODE
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5
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6 Deferring the definitions of the commas, marks, and resolves
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7 allows the same assembler to serve for both the system and the
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8 Meta-Compiler.
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9
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10
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11
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12
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13
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14
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15
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Screen 18 not modified
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0 \ 8086 Assembler Register Definitions 12Oct83map
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1
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2 On the 8086, register names are cleverly defined constants.
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3
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4 The value returned by registers and by modes such as #) contains
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5 both mode and register information. The instructions use the
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6 mode information to decide how many arguments exist, and what to
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7 assemble.
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8 Like many CPUs, the 8086 uses many 3 bit fields in its opcodes
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9 This makes octal ( base 8 ) natural for describing the registers
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10
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11
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12 We redefine the Registers that FORTH uses to implement its
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13 virtual machine.
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14
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15
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Screen 19 not modified
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0 \ Addressing Modes 16Oct83map
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1 MD defines words which test for various modes.
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2 R8? R16? MEM? SEG? #? test for mode equal to 0 thru 4.
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3 REG? tests for any register mode ( 8 or 16 bit).
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4 BIG? tests offsets size. True if won't fit in one byte.
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5 RLOW mask off all but low register field.
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6 RMID mask off all but middle register field.
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7 SIZE true for 16 bit, false for 8 bit.
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8 BYTE set size to 8 bit.
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9 OP, for efficiency. OR two numbers and assemble.
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10 W, assemble opcode with W field set for size of register.
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11 SIZE, assemble opcode with W field set for size of data.
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12 ,/C, assemble either 8 or 16 bits.
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13 RR, assemble register to register instruction.
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14 LOGICAL true while assembling logical instructions.
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15 B/L? see 13MI
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Screen 20 not modified
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0 \ Addressing 16Oct83map
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1 These words perform most of the addressing mode encoding.
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2 MEM, handles memory reference modes. It takes a displacement,
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3 a mode/register, and a register, and encodes and assembles
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4 them.
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5
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6
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7 WMEM, uses MEM, after packing the register size into the opcode
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8 R/M, assembles either a register to register or a register to
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9 or from memory mode.
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10 WR/SM, assembles either a register mode with size field, or a
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11 memory mode with size from SIZE. Default is 16 bit. Use BYTE
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12 for 8 bit size.
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13 INTER true if inter-segment jump, call, or return.
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14 FAR sets INTER true. Usage: FAR JMP, FAR CALL, FAR RET.
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15 ?FAR sets far bit, clears flag.
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Screen 21 not modified
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0 \ Defining Words to Generate Op Codes 12Oct83map
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1 1MI define one byte constant instructions.
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2 2MI define ascii adjust instructions.
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3 3MI define branch instructions, with one byte offset.
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4 4MI define LDS, LEA, LES instructions.
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5 5MI define string instructions.
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6 6MI define more string instructions.
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7 7MI define multiply and divide instructions.
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8 8MI define input and output instructions.
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9
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10 9MI define increment/decrement instructions.
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11
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12 10MI define shift/rotate instructions.
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13 *NOTE* To allow both 'ax shl' and 'ax cl shl', if the register
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14 on top of the stack is cl, shift second register by cl. If not,
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15 shift top ( only) register by one.
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Screen 22 not modified
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0 \ Defining Words to Generate Op Codes 09Apr84map
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1 11MI define calls and jumps.
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2 notice that the first byte stored is E9 for jmp and E8 for call
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3 so C@ 1 AND is zero for call, 1 for jmp.
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4 syntax for direct intersegment: address segment #) FAR JMP
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5
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6
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7
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8 12MI define pushes and pops.
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9
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10
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11
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12
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13 14MI defines returns.
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14 RET FAR RET n +RET n FAR +RET
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15
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Screen 23 not modified
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0 \ Defining Words to Generate Op Codes 16Oct83map
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1 13MI define arithmetic and logical instructions.
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2
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3
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4
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5
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6
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7
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14
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15
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Screen 24 not modified
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0 \ Instructions 16Oct83map
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1 TEST bits in dest
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2
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3
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4
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5
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6
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7
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14
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15
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Screen 25 not modified
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0 \ Instructions 16Oct83map
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1
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2 ESC
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3 INT assemble interrupt instruction.
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4 SEG assemble segment instruction.
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5 XCHG assemble register swap instruction.
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6
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7
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8
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9
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10
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11 CS: DS: ES: SS: assemble segment over-ride instructions.
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12
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13
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14
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15
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Screen 26 not modified
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0 \ Instructions 12Oct83map
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1 MOV as usual, the move instruction is the most complicated.
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2 It allows more addressing modes than any other, each of which
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3 assembles something more or less unique.
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4
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5
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6
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7
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0 \ Instructions 12Oct83map
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1 Most instructions are defined on these two screens. Mnemonics in
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0 \ Instructions 12Oct83map
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1 Most instructions are defined on these two screens. Mnemonics in
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2 parentheses are defined earlier or not at all.
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0 \ Structured Conditionals 16Oct83map
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1 A?>MARK assembler version of forward mark.
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2 A?>RESOLVE assembler version of forward resolve.
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3 A?<MARK assembler version of backward mark.
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4 A?<RESOLVE assembler version of backward resolve.
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12 For example,
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0 \ Structured Conditionals 12Oct83map
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1
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2 One of the very best features of FORTH assemblers is the ability
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3 to use structured conditionals instead of branching to nonsense
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4 labels.
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