2013-04-07 21:29:09 +00:00
|
|
|
;ACME 0.94.4
|
2012-02-27 21:14:46 +00:00
|
|
|
|
|
|
|
!macro cmp16bit .data1, .data2 {
|
|
|
|
ldx #.data1
|
|
|
|
ldy #.data2
|
|
|
|
jsr cmp16bit
|
|
|
|
}
|
|
|
|
a = 0
|
|
|
|
x = 1
|
|
|
|
y = 2
|
|
|
|
|
|
|
|
!macro bank .r, .v {
|
|
|
|
!if .r = a {
|
|
|
|
lda #.v
|
|
|
|
sta conreg
|
|
|
|
}
|
|
|
|
!if .r = x {
|
|
|
|
ldx #.v
|
|
|
|
stx conreg
|
|
|
|
}
|
|
|
|
!if .r = y {
|
|
|
|
ldy #.v
|
|
|
|
sty conreg
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
CR_BANK15 = 0
|
|
|
|
CR_RAM0_IO = $3e
|
|
|
|
CR_RAM0 = $3f
|
|
|
|
|
|
|
|
!macro bank15 {
|
|
|
|
+bank a, CR_BANK15
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro xbank15 {
|
|
|
|
+bank x, CR_BANK15
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro ybank15 {
|
|
|
|
+bank y, CR_BANK15
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro ram0io {
|
|
|
|
+bank a, CR_RAM0_IO
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro yram0io {
|
|
|
|
+bank y, CR_RAM0_IO
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro xram0 {
|
|
|
|
+bank x, CR_RAM0
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro inc16x .a {
|
2013-04-07 21:29:09 +00:00
|
|
|
inc .a, x
|
2012-02-27 21:14:46 +00:00
|
|
|
bne +
|
2013-04-07 21:29:09 +00:00
|
|
|
inc .a + 1, x
|
2012-02-27 21:14:46 +00:00
|
|
|
+
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro ldax .a {
|
2013-04-07 21:29:09 +00:00
|
|
|
lda .a + 1
|
2012-02-27 21:14:46 +00:00
|
|
|
ldx .a
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro cp16 .s, .t {
|
|
|
|
ldx .s
|
2013-04-07 21:29:09 +00:00
|
|
|
lda .s + 1
|
2012-02-27 21:14:46 +00:00
|
|
|
stx .t
|
2013-04-07 21:29:09 +00:00
|
|
|
sta .t + 1
|
|
|
|
}
|
|
|
|
|
|
|
|
!macro wait_for_vdc {
|
|
|
|
- bit vdc
|
|
|
|
bpl -
|
2012-02-27 21:14:46 +00:00
|
|
|
}
|