2020-06-29 15:10:42 +00:00
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m65 opcode table(s)
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The m65 instruction set extends the 4502 instruction set using prefix bytes.
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Therefore, the "normal" opcode table is the same as for the 4502 cpu (see that
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file), so this file only contains information about the extensions.
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"quad mode" allows 32-bit data operations using a virtual register called 'Q'.
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2020-06-30 09:24:30 +00:00
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The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes.
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The mnemonics ldq/stq have nine addressing modes in quad mode, and a tenth
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when combined with long mode.
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2020-06-29 15:10:42 +00:00
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The mnemonics cpq/adcq/sbcq/andq/eorq/orq have eight addressing modes in quad
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2020-06-30 09:24:30 +00:00
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mode, and a ninth when combined with long mode.
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2020-06-29 15:10:42 +00:00
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This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
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then taken from this table:
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00 01 orq (zp, x) 02 03
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04 05 orq zp 06 aslq zp 07
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08 09 0a aslq 0b
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0c 0d orq abs16 0e aslq abs16 0f
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10 11 orq (zp), y 12 orq (zp) 13
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14 15 orq zp, x 16 aslq zp, x 17
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18 19 orq abs16, y 1a inq 1b
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1c 1d orq abs16, x 1e aslq abs16, x 1f
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20 21 andq (zp, x) 22 23
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24 25 andq zp 26 rolq zp 27
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28 29 2a rolq 2b
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2c 2d andq abs16 2e rolq abs16 2f
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30 31 andq (zp), y 32 andq (zp) 33
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34 35 andq zp, x 36 rolq zp, x 37
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38 39 andq abs16, y 3a deq 3b
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3c 3d andq abs16, x 3e rolq abs16, x 3f
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40 41 eorq (zp, x) 42 43
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44 45 eorq zp 46 lsrq zp 47
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48 49 4a lsrq 4b
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4c 4d eorq abs16 4e lsrq abs16 4f
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50 51 eorq (zp), y 52 eorq (zp) 53
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54 55 eorq zp, x 56 lsrq zp, x 57
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58 59 eorq abs16, y 5a 5b
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5c 5d eorq abs16, x 5e lsrq abs16, x 5f
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60 61 adcq (zp, x) 62 63
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64 65 adcq zp 66 rorq zp 67
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68 69 6a rorq 6b
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6c 6d adcq abs16 6e rorq abs16 6f
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70 71 adcq (zp), y 72 adcq (zp) 73
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74 75 adcq zp, x 76 rorq zp, x 77
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78 79 adcq abs16, y 7a 7b
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7c 7d adcq abs16, x 7e rorq abs16, x 7f
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80 81 stq (zp, x) 82 stq (zp, s), y 83
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84 85 stq zp 86 87
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88 89 8a 8b
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8c 8d stq abs16 8e 8f
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90 91 stq (zp), y 92 stq (zp) 93
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94 95 stq zp, x 96 97
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98 99 stq abs16, y 9a 9b
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9c 9d stq abs16, x 9e 9f
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a0 a1 ldq (zp, x) a2 a3
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a4 a5 ldq zp a6 a7
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a8 a9 aa ab
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ac ad ldq abs16 ae af
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b0 b1 ldq (zp), y b2 ldq (zp) b3
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b4 b5 ldq zp, x b6 b7
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b8 b9 ldq abs16, y ba bb
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bc bd ldq abs16, x be bf
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c0 c1 cpq (zp, x) c2 c3
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c4 c5 cpq zp c6 deq zp c7
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c8 c9 ca cb
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cc cd cpq abs16 ce deq abs16 cf
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d0 d1 cpq (zp), y d2 cpq (zp) d3
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d4 d5 cpq zp, x d6 deq zp, x d7
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d8 d9 cpq abs16, y da db
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dc dd cpq abs16, x de deq abs16, x df
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e0 e1 sbcq (zp, x) e2 ldq (zp, s), y e3
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e4 e5 sbcq zp e6 inq zp e7
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e8 e9 ea eb
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ec ed sbcq abs16 ee inq abs16 ef
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f0 f1 sbcq (zp), y f2 sbcq (zp) f3
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f4 f5 sbcq zp, x f6 inq zp, x f7
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f8 f9 sbcq abs16, y fa fb
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fc fd sbcq abs16, x fe inq abs16, x ff
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zp: 8-bit zeropage address
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abs16: 16-bit absolute address
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"long mode" adds an addressing mode using 32-bit pointers for eight existing
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mnemonics. This mode is entered after a NOP (ea) prefix, the following opcode
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should then be one of these:
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12 ora [zp], z 32 and [zp], z 52 eor [zp], z 72 adc [zp], z
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92 sta [zp], z b2 lda [zp], z d2 cmp [zp], z f2 sbc [zp], z
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"quad" and "long" modes can be combined to have 32-bit data access using a
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32-bit pointer. This adds another addressing mode for eight of the new
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mnemonics. This mode is entered after a NEG:NEG:NOP (42 42 ea) prefix, the
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following opcode should then be one of these:
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12 orq [zp] 32 andq [zp] 52 eorq [zp] 72 adcq [zp]
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92 stq [zp] b2 ldq [zp] d2 cpq [zp] f2 sbcq [zp]
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Because the addressing modes are changed a bit by the prefix codes, here are
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some of the unsupported combinations just for comparison (these result in
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"Illegal combination of command and addressing mode"):
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lda (zp) ; 65c02 knew this, but 65ce02 added z index!
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lda [zp] ; long mode also expects z index!
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ldq #imm ; quad mode has no immediate addressing!
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ldq (zp), z ; quad mode does not use z index!
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ldq [zp], z ; quad and long modes combined do not use z index!
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