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tweaked docs
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@80 4df02467-bbd4-4a76-a152-e7ce94205b78
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@ -6,7 +6,7 @@
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- free software -
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(C) 1998-2014 Marco Baye
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(C) 1998-2016 Marco Baye
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----------------------------------------------------------------------
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@ -14,7 +14,7 @@ Section: Copyright
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----------------------------------------------------------------------
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ACME - a crossassembler for producing 6502/6510/65c02/65816 code.
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Copyright (C) 1998-2014 Marco Baye
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Copyright (C) 1998-2016 Marco Baye
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The ACME icon was designed by Wanja "Brix" Gayk
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This program is free software; you can redistribute it and/or modify
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@ -64,6 +64,7 @@ The files in the docs directory and what they contain:
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QuickRef.txt All the basic stuff about ACME
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Source.txt How to compile ACME
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Upgrade.txt Incompatibilities to earlier versions
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cputypes.txt Instruction sets of target CPUs
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IMPORTANT: If you upgrade from ACME 0.05 or earlier, don't forget to
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read the file "Upgrade.txt" - release 0.07 and all later ones are
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@ -17,7 +17,8 @@ ACME supports the following cpu types:
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This is the instruction set of the original NMOS 6502 designed by MOS
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(later CSG).
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There are 151 documented opcodes.
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ACME does not use "A" to indicate "accumulator addressing"; just write
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the mnemonic without any argument: "LSR" will work, "LSR A" won't.
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@ -36,20 +37,20 @@ See "docs/Illegals.txt" for more info.
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This is the CMOS re-design of the 6502. It seems to have also been
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available from Rockwell, GTE/CMD and others. Features:
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- new instructions:
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BRA (branch always)
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PHX, PHY, PLX, PLY (push/pull X/Y register)
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STZ (store zero, 4 addr modes)
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TRB (test and reset bits, 2 addr modes)
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TSB (test and set bits, 2 addr modes)
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BRA branch always
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PHX/PHY/PLX/PLY push/pull X/Y register
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STZ store zero, 4 addr modes
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TRB test and reset bits, 2 addr modes
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TSB test and set bits, 2 addr modes
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- new addressing modes for existing instructions:
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LDA/STA/ADC/SBC ($12) zp indirect
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AND/ORA/EOR/CMP ($12) zp indirect
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BIT #$12
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BIT $12, x
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BIT $1234, x
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LDA/STA/ADC/SBC ($12) (zp indirect without index)
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AND/ORA/EOR/CMP ($12) (zp indirect without index)
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INC (increment accumulator)
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DEC (decrement accumulator)
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JMP ($1234,x) (jump indexed indirect)
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INC increment accumulator
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DEC decrement accumulator
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JMP ($1234, x) x-indexed indirect
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- bugfix for flags in decimal mode
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- bugfix for JMP($xxff) instruction
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- undocumented opcodes are NOPs (although of different lengths)
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@ -61,10 +62,10 @@ There are 178 documented opcodes.
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This is a superset of 65c02, probably originally from Rockwell.
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- It adds bit manipulation instructions:
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BBR0..BBR7 (branch on bit reset)
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BBS0..BBS7 (branch on bit set)
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RMB0..RMB7 (reset memory bit)
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SMB0..SMB7 (set memory bit)
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BBR0..BBR7 branch on bit reset
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BBS0..BBS7 branch on bit set
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RMB0..RMB7 reset memory bit
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SMB0..SMB7 set memory bit
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Chips with this instruction set seem to have been available from
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Rockwell, GTE/CMD and others.
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There are 210 documented opcodes.
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@ -89,6 +90,7 @@ have been available from GTE/CMD as well). Features:
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- block transfers
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There are 256 documented opcodes, but one of them ("WDM") is reserved
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for future expansion.
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See "docs/65816.txt" for more info.
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@ -103,6 +105,12 @@ This is a superset of r65c02, originating at CSG. Features:
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There is a known bug: SBC does not work correctly in decimal mode.
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There are 256 documented opcodes, but one of them ("AUG") is reserved
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for future expansion.
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ACME uses different mnemonics for old ("near") and new ("far") branch
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instructions:
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BEQ old, 8-bit offset
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LBEQ new, 16-bit offset
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The original datasheet called BRA ("branch always") BRU ("branch
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unconditional") instead. ACME accepts both mnemonics.
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@ -121,7 +129,7 @@ There are 256 documented opcodes.
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This is the cpu in version 2 of the C64DTV. It uses a superset of the
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6502 instruction set. Features:
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- new instructions:
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BRA $1234 (branch always)
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SAC #$12 (set accumulator mapping)
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SIR #$12 (set index register mapping)
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BRA $1234 branch always
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SAC #$12 set accumulator mapping
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SIR #$12 set index register mapping
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- support for some of the undocumented opcodes.
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