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added 65c02 opcode table to docs
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@107 4df02467-bbd4-4a76-a152-e7ce94205b78
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marcobaye
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@ -872,7 +872,7 @@ Parameters: KEYWORD: Currently valid keywords are:
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4502 65ce02 with MAP instead of AUG
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c64dtv2 6502 plus BRA/SAC/SIR plus some of the
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undocumented opcodes
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See "docs/cputypes.txt" for more info.
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See "docs/cputypes/all.txt" for more info.
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BLOCK: A block of assembler statements.
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Examples: !if cputype = $65c02 {
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!cpu 65c02 { ; temporarily allow 65c02 stuff
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@ -6,7 +6,7 @@
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- free software -
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(C) 1998-2017 Marco Baye
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(C) 1998-2019 Marco Baye
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----------------------------------------------------------------------
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@ -64,7 +64,7 @@ The files in the docs directory and what they contain:
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QuickRef.txt All the basic stuff about ACME
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Source.txt How to compile ACME
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Upgrade.txt Incompatibilities to earlier versions
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cputypes.txt Instruction sets of target CPUs
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cputypes/ Instruction sets of target CPUs
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IMPORTANT: If you upgrade from ACME 0.05 or earlier, don't forget to
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read the file "Upgrade.txt" - release 0.07 and all later ones are
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130
docs/cputypes/cpu 65c02.txt
Normal file
130
docs/cputypes/cpu 65c02.txt
Normal file
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@ -0,0 +1,130 @@
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65c02 opcode table
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All empty entries are undocumented opcodes.
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Notice there are still no documented opcodes in the fourth column.
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All differences to the original 6502 are marked using a '+' sign.
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00 brk 01 ora (zp, x) 02 03
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04+ tsb zp 05 ora zp 06 asl zp 07
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08 php 09 ora #imm8 0a asl 0b
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0c+ tsb abs16 0d ora abs16 0e asl abs16 0f
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10 bpl rel8 11 ora (zp), y 12+ ora (zp) 13
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14+ trb zp 15 ora zp, x 16 asl zp, x 17
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18 clc 19 ora abs16, y 1a+ inc 1b
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1c+ trb abs16 1d ora abs16, x 1e asl abs16, x 1f
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20 jsr abs16 21 and (zp, x) 22 23
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24 bit zp 25 and zp 26 rol zp 27
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28 plp 29 and #imm8 2a rol 2b
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2c bit abs16 2d and abs16 2e rol abs16 2f
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30 bmi rel8 31 and (zp), y 32+ and (zp) 33
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34+ bit zp, x 35 and zp, x 36 rol zp, x 37
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38 sec 39 and abs16, y 3a+ dec 3b
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3c+ bit abs16, x 3d and abs16, x 3e rol abs16, x 3f
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40 rti 41 eor (zp, x) 42 43
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44 45 eor zp 46 lsr zp 47
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48 pha 49 eor #imm8 4a lsr 4b
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4c jmp abs16 4d eor abs16 4e lsr abs16 4f
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50 bvc rel8 51 eor (zp), y 52+ eor (zp) 53
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54 55 eor zp, x 56 lsr zp, x 57
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58 cli 59 eor abs16, y 5a+ phy 5b
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5c 5d eor abs16, x 5e lsr abs16, x 5f
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60 rts 61 adc (zp, x) 62 63
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64+ stz zp 65 adc zp 66 ror zp 67
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68 pla 69 adc #imm8 6a ror 6b
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6c jmp (abs16) 6d adc abs16 6e ror abs16 6f
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70 bvs rel8 71 adc (zp), y 72+ adc (zp) 73
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74+ stz zp, x 75 adc zp, x 76 ror zp, x 77
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78 sei 79 adc abs16, y 7a+ ply 7b
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7c+ jmp (abs16, x) 7d adc abs16, x 7e ror abs16, x 7f
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80+ bra rel8 81 sta (zp, x) 82 83
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84 sty zp 85 sta zp 86 stx zp 87
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88 dey 89+ bit #imm8 8a txa 8b
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8c sty abs16 8d sta abs16 8e stx abs16 8f
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90 bcc rel8 91 sta (zp), y 92+ sta (zp) 93
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94 sty zp, x 95 sta zp, x 96 stx zp, y 97
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98 tya 99 sta abs16, y 9a txs 9b
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9c+ stz abs16 9d sta abs16, x 9e+ stz abs16, x 9f
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a0 ldy #imm8 a1 lda (zp, x) a2 ldx #imm8 a3
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a4 ldy zp a5 lda zp a6 ldx zp a7
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a8 tay a9 lda #imm8 aa tax ab
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ac ldy abs16 ad lda abs16 ae ldx abs16 af
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b0 bcs rel8 b1 lda (zp), y b2+ lda (zp) b3
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b4 ldy zp, x b5 lda zp, x b6 ldx zp, y b7
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b8 clv b9 lda abs16, y ba tsx bb
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bc ldy abs16, x bd lda abs16, x be ldx abs16, y bf
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c0 cpy #imm8 c1 cmp (zp, x) c2 c3
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c4 cpy zp c5 cmp zp c6 dec zp c7
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c8 iny c9 cmp #imm8 ca dex cb
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cc cpy abs16 cd cmp abs16 ce dec abs16 cf
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d0 bne rel8 d1 cmp (zp), y d2+ cmp (zp) d3
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d4 d5 cmp zp, x d6 dec zp, x d7
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d8 cld d9 cmp abs16, y da+ phx db
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dc dd cmp abs16, x de dec abs16, x df
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e0 cpx #imm8 e1 sbc (zp, x) e2 e3
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e4 cpx zp e5 sbc zp e6 inc zp e7
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e8 inx e9 sbc #imm8 ea nop eb
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ec cpx abs16 ed sbc abs16 ee inc abs16 ef
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f0 beq rel8 f1 sbc (zp), y f2+ sbc (zp) f3
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f4 f5 sbc zp, x f6 inc zp, x f7
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f8 sed f9 sbc abs16, y fa+ plx fb
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fc fd sbc abs16, x fe inc abs16, x ff
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#imm8: 8-bit immediate value
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zp: 8-bit zeropage address
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abs16: 16-bit absolute address
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rel8: 8-bit relative address offset
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The 65c02 is the CMOS re-design of the 6502. It has a few
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improvements:
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New mnemonics
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-------------
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test and (re-)set bits against accumulator:
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04 tsb zp
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0c tsb abs16
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14 trb zp
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1c trb abs16
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push/pull x/y:
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5a phy
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7a ply
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da phx
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fa plx
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store zero:
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64 stz zp
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74 stz zp, x
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9c stz abs16
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9e stz abs16, x
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branch always:
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80 bra rel8
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New addressing modes for existing mnemonics
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-------------------------------------------
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zp indirect addressing without indexing:
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12 ora (zp)
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32 and (zp)
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52 eor (zp)
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72 adc (zp)
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92 sta (zp)
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b2 lda (zp)
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d2 cmp (zp)
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f2 sbc (zp)
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implied ("accumulator") addressing:
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1a inc
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3a dec
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x-indexed indirect addressing:
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7c jmp (abs16, x)
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three more addressing modes for BIT:
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34 bit zp, x
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3c bit abs16, x
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89 bit #imm8
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