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fixed addressing modes for M65 cpu (see tickets 22 and 23)
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@436 4df02467-bbd4-4a76-a152-e7ce94205b78
This commit is contained in:
marcobaye
@@ -178,7 +178,8 @@ Features:
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- "quad mode" (32-bit data operations on virtual register 'Q')
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- "long mode" (32-bit pointer addressing for existing mnemonics)
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- "quad" and "long" modes can be combined
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quad mode introduces several new mnemonics:
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"quad" mode introduces several new mnemonics:
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LDQ/STQ/CPQ like LDA/STA/CMP
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ADCQ/SBCQ like ADC/SBC
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ANDQ/EORQ/ORQ like AND/EOR/ORA
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@@ -189,10 +190,11 @@ quad mode introduces several new mnemonics:
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The new mnemonics support most of the addressing modes of the
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original mnemonics with these exceptions:
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- there is no immediate addressing
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- indirect-Z-indexed addressing becomes indirect addressing
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- indirect-Z-indexed addressing becomes indirect addressing,
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except for LDQ.
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- all other indexed addressing modes can only really be used
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with read-modify-write instructions or LDQ, because otherwise
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a part of the 'Q' value would be used as the index.
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with read-modify-write instructions, because otherwise a part
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of the 'Q' value would be used as the index.
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CAUTION: The STQ instruction clobbers the N and Z flags!
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There is no "real" Q register, instead A/X/Y/Z are combined to form
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the Q register (A holds lsb, Z holds msb), except for read-modify-
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@@ -200,7 +202,8 @@ quad mode introduces several new mnemonics:
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using A/X/Y/Z.
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To load a 32-bit immediate constant into the Q register, use the
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+movq macro from the <m65/std.a> library file.
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long mode brings a single new addressing mode for eight mnemonics:
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"long" mode brings a single new addressing mode for eight mnemonics:
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LDA [$12], z contents of $12/$13/$14/$15
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STA [$12], z plus z form the address
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CMP [$12], z
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@@ -209,9 +212,10 @@ long mode brings a single new addressing mode for eight mnemonics:
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AND [$12], z
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EOR [$12], z
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ORA [$12], z
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quad and long modes combined result in another addressing mode for
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"quad" and "long" modes combined result in another addressing mode for
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eight of the new mnemonics:
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LDQ [$12] contents of $12/$13/$14/$15
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LDQ [$12], z contents of $12/$13/$14/$15
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STQ [$12] form the address
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CPQ [$12]
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ADCQ [$12]
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@@ -219,6 +223,7 @@ quad and long modes combined result in another addressing mode for
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ANDQ [$12]
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EORQ [$12]
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ORQ [$12]
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The NOP mnemonic is disabled for this instruction set because its
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opcode is re-used internally as a prefix byte.
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CAUTION: The !align pseudo opcode still inserts NOPs.
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@@ -8,10 +8,8 @@ file), so this file only contains information about the extensions.
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"quad mode" allows 32-bit data operations using a virtual register called 'Q'.
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The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes.
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The mnemonic ldq has eight addressing modes in quad mode, and a ninth when
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combined with long mode.
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The mnemonics stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes in
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quad mode, and a fourth when combined with long mode.
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The mnemonics ldq/stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes
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in quad mode, and a fourth when combined with long mode.
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The mnemonic bitq has two addressing modes.
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The mnemonic asrq has three addressing modes.
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This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
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@@ -66,10 +64,10 @@ a0 a1 a2 a3
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a4 a5 ldq zp a6 a7
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a8 a9 aa ab
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ac ad ldq abs16 ae af
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b0 b1 ldq (zp), y b2 ldq (zp) b3
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b4 b5 ldq zp, x b6 b7
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b8 b9 ldq abs16, y ba bb
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bc bd ldq abs16, x be bf
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b0 b1 b2 ldq (zp), z b3
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b4 b5 b6 b7
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b8 b9 ba bb
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bc bd be bf
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c0 c1 c2 c3
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c4 c5 cpq zp c6 deq zp c7
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@@ -80,7 +78,7 @@ d4 d5 d6 deq zp, x d7
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d8 d9 da db
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dc dd de deq abs16, x df
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e0 e1 e2 ldq (zp, s), y e3
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e0 e1 e2 e3
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e4 e5 sbcq zp e6 inq zp e7
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e8 e9 ea eb
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ec ed sbcq abs16 ee inq abs16 ef
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@@ -107,7 +105,7 @@ mnemonics. This mode is entered after a NEG:NEG:NOP (42 42 ea) prefix, the
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following opcode should then be one of these:
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12 orq [zp] 32 andq [zp] 52 eorq [zp] 72 adcq [zp]
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92 stq [zp] b2 ldq [zp] d2 cpq [zp] f2 sbcq [zp]
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92 stq [zp] b2 ldq [zp], z d2 cpq [zp] f2 sbcq [zp]
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Because the addressing modes are changed a bit by the prefix codes, here are
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@@ -116,5 +114,7 @@ some of the unsupported combinations just for comparison (these result in
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lda (zp) ; 65c02 knew this, but 65ce02 added z index!
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lda [zp] ; long mode also expects z index!
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ldq #imm ; quad mode has no immediate addressing!
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ldq (zp), z ; quad mode does not use z index!
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ldq [zp], z ; quad and long modes combined do not use z index!
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stq (zp), z ; quad mode only uses z index for LDQ!
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stq [zp], z ; quad+long mode only uses z index for LDQ!
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ldq (zp) ; LDQ uses z index!
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ldq [zp] ; LDQ in long mode uses z index!
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16
src/mnemo.c
16
src/mnemo.c
@@ -96,17 +96,17 @@ enum mnemogroup {
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enum { IDX_ORA,IDXcORA,IDX16ORA,IDXeORA,IDXmORA,IDXmORQ,IDX_AND,IDXcAND,IDX16AND,IDXeAND,IDXmAND,IDXmANDQ,IDX_EOR,IDXcEOR,IDX16EOR,IDXeEOR,IDXmEOR,IDXmEORQ,IDX_ADC,IDXcADC,IDX16ADC,IDXeADC,IDXmADC,IDXmADCQ,IDX_STA,IDXcSTA,IDX16STA,IDXeSTA,IDXmSTA,IDXmSTQ,IDX_LDA,IDXcLDA,IDX16LDA,IDXeLDA,IDXmLDA,IDXmLDQ,IDX_CMP,IDXcCMP,IDX16CMP,IDXeCMP,IDXmCMP,IDXmCPQ,IDX_SBC,IDXcSBC,IDX16SBC,IDXeSBC,IDXmSBC,IDXmSBCQ,IDX16PEI,IDXuSLO,IDXuRLA,IDXuSRE,IDXuRRA,IDXuSAX,IDXuLAX,IDXuDCP,IDXuISC,IDXuSHA};
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SCB accu_imm[] = { 0x09, 0x09, 0x09, 0x09, 0x09, 0, 0x29, 0x29, 0x29, 0x29, 0x29, 0, 0x49, 0x49, 0x49, 0x49, 0x49, 0, 0x69, 0x69, 0x69, 0x69, 0x69, 0, 0, 0, 0, 0, 0, 0, 0xa9, 0xa9, 0xa9, 0xa9, 0xa9, 0, 0xc9, 0xc9, 0xc9, 0xc9, 0xc9, 0, 0xe9, 0xe9, 0xe9, 0xe9, 0xe9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // #$ff #$ffff
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SCL accu_abs[] = { 0x0d05, 0x0d05,0x0f0d05, 0x0d05, 0x0d05, 0x0d05, 0x2d25, 0x2d25,0x2f2d25, 0x2d25, 0x2d25, 0x2d25, 0x4d45, 0x4d45,0x4f4d45, 0x4d45, 0x4d45, 0x4d45, 0x6d65, 0x6d65,0x6f6d65, 0x6d65, 0x6d65, 0x6d65, 0x8d85, 0x8d85,0x8f8d85, 0x8d85, 0x8d85, 0x8d85, 0xada5, 0xada5,0xafada5, 0xada5, 0xada5, 0xada5, 0xcdc5, 0xcdc5,0xcfcdc5, 0xcdc5, 0xcdc5, 0xcdc5, 0xede5, 0xede5,0xefede5, 0xede5, 0xede5, 0xede5, 0, 0x0f07, 0x2f27, 0x4f47, 0x6f67, 0x8f87, 0xafa7, 0xcfc7, 0xefe7, 0}; // $ff $ffff $ffffff
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SCL accu_xabs[] = { 0x1d15, 0x1d15,0x1f1d15, 0x1d15, 0x1d15, 0, 0x3d35, 0x3d35,0x3f3d35, 0x3d35, 0x3d35, 0, 0x5d55, 0x5d55,0x5f5d55, 0x5d55, 0x5d55, 0, 0x7d75, 0x7d75,0x7f7d75, 0x7d75, 0x7d75, 0, 0x9d95, 0x9d95,0x9f9d95, 0x9d95, 0x9d95, 0, 0xbdb5, 0xbdb5,0xbfbdb5, 0xbdb5, 0xbdb5, 0xbdb5, 0xddd5, 0xddd5,0xdfddd5, 0xddd5, 0xddd5, 0, 0xfdf5, 0xfdf5,0xfffdf5, 0xfdf5, 0xfdf5, 0, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x
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SCS accu_yabs[] = { 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y
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SCL accu_xabs[] = { 0x1d15, 0x1d15,0x1f1d15, 0x1d15, 0x1d15, 0, 0x3d35, 0x3d35,0x3f3d35, 0x3d35, 0x3d35, 0, 0x5d55, 0x5d55,0x5f5d55, 0x5d55, 0x5d55, 0, 0x7d75, 0x7d75,0x7f7d75, 0x7d75, 0x7d75, 0, 0x9d95, 0x9d95,0x9f9d95, 0x9d95, 0x9d95, 0, 0xbdb5, 0xbdb5,0xbfbdb5, 0xbdb5, 0xbdb5, 0, 0xddd5, 0xddd5,0xdfddd5, 0xddd5, 0xddd5, 0, 0xfdf5, 0xfdf5,0xfffdf5, 0xfdf5, 0xfdf5, 0, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x
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SCS accu_yabs[] = { 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y
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SCB accu_xind8[] = { 0x01, 0x01, 0x01, 0x01, 0x01, 0, 0x21, 0x21, 0x21, 0x21, 0x21, 0, 0x41, 0x41, 0x41, 0x41, 0x41, 0, 0x61, 0x61, 0x61, 0x61, 0x61, 0, 0x81, 0x81, 0x81, 0x81, 0x81, 0, 0xa1, 0xa1, 0xa1, 0xa1, 0xa1, 0, 0xc1, 0xc1, 0xc1, 0xc1, 0xc1, 0, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0}; // ($ff,x)
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SCB accu_indy8[] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0, 0x31, 0x31, 0x31, 0x31, 0x31, 0, 0x51, 0x51, 0x51, 0x51, 0x51, 0, 0x71, 0x71, 0x71, 0x71, 0x71, 0, 0x91, 0x91, 0x91, 0x91, 0x91, 0, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y
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SCB accu_ind8[] = { 0, 0x12, 0x12, 0, 0, 0x12, 0, 0x32, 0x32, 0, 0, 0x32, 0, 0x52, 0x52, 0, 0, 0x52, 0, 0x72, 0x72, 0, 0, 0x72, 0, 0x92, 0x92, 0, 0, 0x92, 0, 0xb2, 0xb2, 0, 0, 0xb2, 0, 0xd2, 0xd2, 0, 0, 0xd2, 0, 0xf2, 0xf2, 0, 0, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff)
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SCB accu_indy8[] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0, 0x31, 0x31, 0x31, 0x31, 0x31, 0, 0x51, 0x51, 0x51, 0x51, 0x51, 0, 0x71, 0x71, 0x71, 0x71, 0x71, 0, 0x91, 0x91, 0x91, 0x91, 0x91, 0, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y
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SCB accu_ind8[] = { 0, 0x12, 0x12, 0, 0, 0x12, 0, 0x32, 0x32, 0, 0, 0x32, 0, 0x52, 0x52, 0, 0, 0x52, 0, 0x72, 0x72, 0, 0, 0x72, 0, 0x92, 0x92, 0, 0, 0x92, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0xd2, 0, 0xf2, 0xf2, 0, 0, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff)
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SCB accu_sabs8[] = { 0, 0, 0x03, 0, 0, 0, 0, 0, 0x23, 0, 0, 0, 0, 0, 0x43, 0, 0, 0, 0, 0, 0x63, 0, 0, 0, 0, 0, 0x83, 0, 0, 0, 0, 0, 0xa3, 0, 0, 0, 0, 0, 0xc3, 0, 0, 0, 0, 0, 0xe3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff,s
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SCB accu_sindy8[] = { 0, 0, 0x13, 0, 0, 0, 0, 0, 0x33, 0, 0, 0, 0, 0, 0x53, 0, 0, 0, 0, 0, 0x73, 0, 0, 0, 0, 0, 0x93, 0x82, 0x82, 0, 0, 0, 0xb3, 0xe2, 0xe2, 0xe2, 0, 0, 0xd3, 0, 0, 0, 0, 0, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y
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SCB accu_lind8[] = { 0, 0, 0x07, 0, 0, 0x12, 0, 0, 0x27, 0, 0, 0x32, 0, 0, 0x47, 0, 0, 0x52, 0, 0, 0x67, 0, 0, 0x72, 0, 0, 0x87, 0, 0, 0x92, 0, 0, 0xa7, 0, 0, 0xb2, 0, 0, 0xc7, 0, 0, 0xd2, 0, 0, 0xe7, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff]
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SCB accu_sindy8[] = { 0, 0, 0x13, 0, 0, 0, 0, 0, 0x33, 0, 0, 0, 0, 0, 0x53, 0, 0, 0, 0, 0, 0x73, 0, 0, 0, 0, 0, 0x93, 0x82, 0x82, 0, 0, 0, 0xb3, 0xe2, 0xe2, 0, 0, 0, 0xd3, 0, 0, 0, 0, 0, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y
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SCB accu_lind8[] = { 0, 0, 0x07, 0, 0, 0x12, 0, 0, 0x27, 0, 0, 0x32, 0, 0, 0x47, 0, 0, 0x52, 0, 0, 0x67, 0, 0, 0x72, 0, 0, 0x87, 0, 0, 0x92, 0, 0, 0xa7, 0, 0, 0, 0, 0, 0xc7, 0, 0, 0xd2, 0, 0, 0xe7, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff]
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SCB accu_lindy8[] = { 0, 0, 0x17, 0, 0, 0, 0, 0, 0x37, 0, 0, 0, 0, 0, 0x57, 0, 0, 0, 0, 0, 0x77, 0, 0, 0, 0, 0, 0x97, 0, 0, 0, 0, 0, 0xb7, 0, 0, 0, 0, 0, 0xd7, 0, 0, 0, 0, 0, 0xf7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],y
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SCB accu_indz8[] = { 0, 0, 0, 0x12, 0x12, 0, 0, 0, 0, 0x32, 0x32, 0, 0, 0, 0, 0x52, 0x52, 0, 0, 0, 0, 0x72, 0x72, 0, 0, 0, 0, 0x92, 0x92, 0, 0, 0, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0, 0, 0xf2, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff),z
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SCB accu_lindz8[] = { 0, 0, 0, 0, 0x12, 0, 0, 0, 0, 0, 0x32, 0, 0, 0, 0, 0, 0x52, 0, 0, 0, 0, 0, 0x72, 0, 0, 0, 0, 0, 0x92, 0, 0, 0, 0, 0, 0xb2, 0, 0, 0, 0, 0, 0xd2, 0, 0, 0, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],z (encoded as a NOP plus ($ff),z)
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SCB accu_indz8[] = { 0, 0, 0, 0x12, 0x12, 0, 0, 0, 0, 0x32, 0x32, 0, 0, 0, 0, 0x52, 0x52, 0, 0, 0, 0, 0x72, 0x72, 0, 0, 0, 0, 0x92, 0x92, 0, 0, 0, 0, 0xb2, 0xb2, 0xb2, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0, 0, 0xf2, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff),z
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SCB accu_lindz8[] = { 0, 0, 0, 0, 0x12, 0, 0, 0, 0, 0, 0x32, 0, 0, 0, 0, 0, 0x52, 0, 0, 0, 0, 0, 0x72, 0, 0, 0, 0, 0, 0x92, 0, 0, 0, 0, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0, 0, 0, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],z (encoded as a NOP plus ($ff),z)
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// Code tables for group GROUP_MISC:
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// These tables are needed for finding out the correct code in cases when
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@@ -9,8 +9,8 @@
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#define RELEASE "0.97" // update before release FIXME
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#define CODENAME "Zem" // update before release
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#define CHANGE_DATE "23 Nov" // update before release FIXME
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#define CHANGE_YEAR "2024" // update before release
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#define CHANGE_DATE "4 May" // update before release FIXME
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#define CHANGE_YEAR "2025" // update before release
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//#define HOME_PAGE "http://home.pages.de/~mac_bacon/smorbrod/acme/"
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#define HOME_PAGE "http://sourceforge.net/p/acme-crossass/" // FIXME
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Binary file not shown.
@@ -87,11 +87,11 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65
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;ldq ($01, x) ; a1
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ldq $05 ; a5
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ldq $0d0e ; ad
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ldq ($11), y ; b1
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ldq ($12) ; b2
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ldq $15, x ; b5
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ldq $1919, y ; b9
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ldq $1d1e, x ; bd
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;ldq ($11), y ; b1
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ldq ($12), z ; b2
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;ldq $15, x ; b5
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;ldq $1919, y ; b9
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;ldq $1d1e, x ; bd
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||||
;cpq ($01, x) ; c1
|
||||
cpq $05 ; c5
|
||||
deq $05 ; c6
|
||||
@@ -105,7 +105,7 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65
|
||||
;cpq $1d1e, x ; dd
|
||||
deq $1d1e, x ; de
|
||||
;sbcq ($01, x) ; e1
|
||||
ldq ($e2, s), y ; e2
|
||||
;ldq ($e2, s), y ; e2
|
||||
sbcq $05 ; e5
|
||||
inq $05 ; e6
|
||||
sbcq $0d0e ; ed
|
||||
@@ -132,6 +132,6 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65
|
||||
eorq [$12] ; 52
|
||||
adcq [$12] ; 72
|
||||
stq [$12] ; 92
|
||||
ldq [$12] ; b2
|
||||
ldq [$12], z ; b2
|
||||
cpq [$12] ; d2
|
||||
sbcq [$12] ; f2
|
||||
|
||||
Reference in New Issue
Block a user