From 8647561ac00f7954dcec53141a8c9afbcdf1f11e Mon Sep 17 00:00:00 2001 From: marcobaye Date: Wed, 7 May 2025 11:08:18 +0000 Subject: [PATCH] fixed addressing modes for M65 cpu (see tickets 22 and 23) git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@436 4df02467-bbd4-4a76-a152-e7ce94205b78 --- docs/cputypes/all.txt | 19 ++++++++++++------- docs/cputypes/cpu m65.txt | 24 ++++++++++++------------ src/mnemo.c | 16 ++++++++-------- src/version.h | 4 ++-- testing/cpus/out-m65.exp | Bin 889 -> 867 bytes testing/cpus/test-m65.a | 14 +++++++------- 6 files changed, 41 insertions(+), 36 deletions(-) diff --git a/docs/cputypes/all.txt b/docs/cputypes/all.txt index 2c7864c..7b394a4 100644 --- a/docs/cputypes/all.txt +++ b/docs/cputypes/all.txt @@ -178,7 +178,8 @@ Features: - "quad mode" (32-bit data operations on virtual register 'Q') - "long mode" (32-bit pointer addressing for existing mnemonics) - "quad" and "long" modes can be combined -quad mode introduces several new mnemonics: + +"quad" mode introduces several new mnemonics: LDQ/STQ/CPQ like LDA/STA/CMP ADCQ/SBCQ like ADC/SBC ANDQ/EORQ/ORQ like AND/EOR/ORA @@ -189,10 +190,11 @@ quad mode introduces several new mnemonics: The new mnemonics support most of the addressing modes of the original mnemonics with these exceptions: - there is no immediate addressing - - indirect-Z-indexed addressing becomes indirect addressing + - indirect-Z-indexed addressing becomes indirect addressing, + except for LDQ. - all other indexed addressing modes can only really be used - with read-modify-write instructions or LDQ, because otherwise - a part of the 'Q' value would be used as the index. + with read-modify-write instructions, because otherwise a part + of the 'Q' value would be used as the index. CAUTION: The STQ instruction clobbers the N and Z flags! There is no "real" Q register, instead A/X/Y/Z are combined to form the Q register (A holds lsb, Z holds msb), except for read-modify- @@ -200,7 +202,8 @@ quad mode introduces several new mnemonics: using A/X/Y/Z. To load a 32-bit immediate constant into the Q register, use the +movq macro from the library file. -long mode brings a single new addressing mode for eight mnemonics: + +"long" mode brings a single new addressing mode for eight mnemonics: LDA [$12], z contents of $12/$13/$14/$15 STA [$12], z plus z form the address CMP [$12], z @@ -209,9 +212,10 @@ long mode brings a single new addressing mode for eight mnemonics: AND [$12], z EOR [$12], z ORA [$12], z -quad and long modes combined result in another addressing mode for + +"quad" and "long" modes combined result in another addressing mode for eight of the new mnemonics: - LDQ [$12] contents of $12/$13/$14/$15 + LDQ [$12], z contents of $12/$13/$14/$15 STQ [$12] form the address CPQ [$12] ADCQ [$12] @@ -219,6 +223,7 @@ quad and long modes combined result in another addressing mode for ANDQ [$12] EORQ [$12] ORQ [$12] + The NOP mnemonic is disabled for this instruction set because its opcode is re-used internally as a prefix byte. CAUTION: The !align pseudo opcode still inserts NOPs. diff --git a/docs/cputypes/cpu m65.txt b/docs/cputypes/cpu m65.txt index 23787d6..9105ea2 100644 --- a/docs/cputypes/cpu m65.txt +++ b/docs/cputypes/cpu m65.txt @@ -8,10 +8,8 @@ file), so this file only contains information about the extensions. "quad mode" allows 32-bit data operations using a virtual register called 'Q'. The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes. -The mnemonic ldq has eight addressing modes in quad mode, and a ninth when -combined with long mode. -The mnemonics stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes in -quad mode, and a fourth when combined with long mode. +The mnemonics ldq/stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes +in quad mode, and a fourth when combined with long mode. The mnemonic bitq has two addressing modes. The mnemonic asrq has three addressing modes. This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is @@ -66,10 +64,10 @@ a0 a1 a2 a3 a4 a5 ldq zp a6 a7 a8 a9 aa ab ac ad ldq abs16 ae af -b0 b1 ldq (zp), y b2 ldq (zp) b3 -b4 b5 ldq zp, x b6 b7 -b8 b9 ldq abs16, y ba bb -bc bd ldq abs16, x be bf +b0 b1 b2 ldq (zp), z b3 +b4 b5 b6 b7 +b8 b9 ba bb +bc bd be bf c0 c1 c2 c3 c4 c5 cpq zp c6 deq zp c7 @@ -80,7 +78,7 @@ d4 d5 d6 deq zp, x d7 d8 d9 da db dc dd de deq abs16, x df -e0 e1 e2 ldq (zp, s), y e3 +e0 e1 e2 e3 e4 e5 sbcq zp e6 inq zp e7 e8 e9 ea eb ec ed sbcq abs16 ee inq abs16 ef @@ -107,7 +105,7 @@ mnemonics. This mode is entered after a NEG:NEG:NOP (42 42 ea) prefix, the following opcode should then be one of these: 12 orq [zp] 32 andq [zp] 52 eorq [zp] 72 adcq [zp] -92 stq [zp] b2 ldq [zp] d2 cpq [zp] f2 sbcq [zp] +92 stq [zp] b2 ldq [zp], z d2 cpq [zp] f2 sbcq [zp] Because the addressing modes are changed a bit by the prefix codes, here are @@ -116,5 +114,7 @@ some of the unsupported combinations just for comparison (these result in lda (zp) ; 65c02 knew this, but 65ce02 added z index! lda [zp] ; long mode also expects z index! ldq #imm ; quad mode has no immediate addressing! - ldq (zp), z ; quad mode does not use z index! - ldq [zp], z ; quad and long modes combined do not use z index! + stq (zp), z ; quad mode only uses z index for LDQ! + stq [zp], z ; quad+long mode only uses z index for LDQ! + ldq (zp) ; LDQ uses z index! + ldq [zp] ; LDQ in long mode uses z index! diff --git a/src/mnemo.c b/src/mnemo.c index 1ed6269..4638305 100644 --- a/src/mnemo.c +++ b/src/mnemo.c @@ -96,17 +96,17 @@ enum mnemogroup { enum { IDX_ORA,IDXcORA,IDX16ORA,IDXeORA,IDXmORA,IDXmORQ,IDX_AND,IDXcAND,IDX16AND,IDXeAND,IDXmAND,IDXmANDQ,IDX_EOR,IDXcEOR,IDX16EOR,IDXeEOR,IDXmEOR,IDXmEORQ,IDX_ADC,IDXcADC,IDX16ADC,IDXeADC,IDXmADC,IDXmADCQ,IDX_STA,IDXcSTA,IDX16STA,IDXeSTA,IDXmSTA,IDXmSTQ,IDX_LDA,IDXcLDA,IDX16LDA,IDXeLDA,IDXmLDA,IDXmLDQ,IDX_CMP,IDXcCMP,IDX16CMP,IDXeCMP,IDXmCMP,IDXmCPQ,IDX_SBC,IDXcSBC,IDX16SBC,IDXeSBC,IDXmSBC,IDXmSBCQ,IDX16PEI,IDXuSLO,IDXuRLA,IDXuSRE,IDXuRRA,IDXuSAX,IDXuLAX,IDXuDCP,IDXuISC,IDXuSHA}; SCB accu_imm[] = { 0x09, 0x09, 0x09, 0x09, 0x09, 0, 0x29, 0x29, 0x29, 0x29, 0x29, 0, 0x49, 0x49, 0x49, 0x49, 0x49, 0, 0x69, 0x69, 0x69, 0x69, 0x69, 0, 0, 0, 0, 0, 0, 0, 0xa9, 0xa9, 0xa9, 0xa9, 0xa9, 0, 0xc9, 0xc9, 0xc9, 0xc9, 0xc9, 0, 0xe9, 0xe9, 0xe9, 0xe9, 0xe9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // #$ff #$ffff SCL accu_abs[] = { 0x0d05, 0x0d05,0x0f0d05, 0x0d05, 0x0d05, 0x0d05, 0x2d25, 0x2d25,0x2f2d25, 0x2d25, 0x2d25, 0x2d25, 0x4d45, 0x4d45,0x4f4d45, 0x4d45, 0x4d45, 0x4d45, 0x6d65, 0x6d65,0x6f6d65, 0x6d65, 0x6d65, 0x6d65, 0x8d85, 0x8d85,0x8f8d85, 0x8d85, 0x8d85, 0x8d85, 0xada5, 0xada5,0xafada5, 0xada5, 0xada5, 0xada5, 0xcdc5, 0xcdc5,0xcfcdc5, 0xcdc5, 0xcdc5, 0xcdc5, 0xede5, 0xede5,0xefede5, 0xede5, 0xede5, 0xede5, 0, 0x0f07, 0x2f27, 0x4f47, 0x6f67, 0x8f87, 0xafa7, 0xcfc7, 0xefe7, 0}; // $ff $ffff $ffffff -SCL accu_xabs[] = { 0x1d15, 0x1d15,0x1f1d15, 0x1d15, 0x1d15, 0, 0x3d35, 0x3d35,0x3f3d35, 0x3d35, 0x3d35, 0, 0x5d55, 0x5d55,0x5f5d55, 0x5d55, 0x5d55, 0, 0x7d75, 0x7d75,0x7f7d75, 0x7d75, 0x7d75, 0, 0x9d95, 0x9d95,0x9f9d95, 0x9d95, 0x9d95, 0, 0xbdb5, 0xbdb5,0xbfbdb5, 0xbdb5, 0xbdb5, 0xbdb5, 0xddd5, 0xddd5,0xdfddd5, 0xddd5, 0xddd5, 0, 0xfdf5, 0xfdf5,0xfffdf5, 0xfdf5, 0xfdf5, 0, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x -SCS accu_yabs[] = { 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y +SCL accu_xabs[] = { 0x1d15, 0x1d15,0x1f1d15, 0x1d15, 0x1d15, 0, 0x3d35, 0x3d35,0x3f3d35, 0x3d35, 0x3d35, 0, 0x5d55, 0x5d55,0x5f5d55, 0x5d55, 0x5d55, 0, 0x7d75, 0x7d75,0x7f7d75, 0x7d75, 0x7d75, 0, 0x9d95, 0x9d95,0x9f9d95, 0x9d95, 0x9d95, 0, 0xbdb5, 0xbdb5,0xbfbdb5, 0xbdb5, 0xbdb5, 0, 0xddd5, 0xddd5,0xdfddd5, 0xddd5, 0xddd5, 0, 0xfdf5, 0xfdf5,0xfffdf5, 0xfdf5, 0xfdf5, 0, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x +SCS accu_yabs[] = { 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y SCB accu_xind8[] = { 0x01, 0x01, 0x01, 0x01, 0x01, 0, 0x21, 0x21, 0x21, 0x21, 0x21, 0, 0x41, 0x41, 0x41, 0x41, 0x41, 0, 0x61, 0x61, 0x61, 0x61, 0x61, 0, 0x81, 0x81, 0x81, 0x81, 0x81, 0, 0xa1, 0xa1, 0xa1, 0xa1, 0xa1, 0, 0xc1, 0xc1, 0xc1, 0xc1, 0xc1, 0, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0}; // ($ff,x) -SCB accu_indy8[] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0, 0x31, 0x31, 0x31, 0x31, 0x31, 0, 0x51, 0x51, 0x51, 0x51, 0x51, 0, 0x71, 0x71, 0x71, 0x71, 0x71, 0, 0x91, 0x91, 0x91, 0x91, 0x91, 0, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y -SCB accu_ind8[] = { 0, 0x12, 0x12, 0, 0, 0x12, 0, 0x32, 0x32, 0, 0, 0x32, 0, 0x52, 0x52, 0, 0, 0x52, 0, 0x72, 0x72, 0, 0, 0x72, 0, 0x92, 0x92, 0, 0, 0x92, 0, 0xb2, 0xb2, 0, 0, 0xb2, 0, 0xd2, 0xd2, 0, 0, 0xd2, 0, 0xf2, 0xf2, 0, 0, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff) +SCB accu_indy8[] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0, 0x31, 0x31, 0x31, 0x31, 0x31, 0, 0x51, 0x51, 0x51, 0x51, 0x51, 0, 0x71, 0x71, 0x71, 0x71, 0x71, 0, 0x91, 0x91, 0x91, 0x91, 0x91, 0, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y +SCB accu_ind8[] = { 0, 0x12, 0x12, 0, 0, 0x12, 0, 0x32, 0x32, 0, 0, 0x32, 0, 0x52, 0x52, 0, 0, 0x52, 0, 0x72, 0x72, 0, 0, 0x72, 0, 0x92, 0x92, 0, 0, 0x92, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0xd2, 0, 0xf2, 0xf2, 0, 0, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff) SCB accu_sabs8[] = { 0, 0, 0x03, 0, 0, 0, 0, 0, 0x23, 0, 0, 0, 0, 0, 0x43, 0, 0, 0, 0, 0, 0x63, 0, 0, 0, 0, 0, 0x83, 0, 0, 0, 0, 0, 0xa3, 0, 0, 0, 0, 0, 0xc3, 0, 0, 0, 0, 0, 0xe3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff,s -SCB accu_sindy8[] = { 0, 0, 0x13, 0, 0, 0, 0, 0, 0x33, 0, 0, 0, 0, 0, 0x53, 0, 0, 0, 0, 0, 0x73, 0, 0, 0, 0, 0, 0x93, 0x82, 0x82, 0, 0, 0, 0xb3, 0xe2, 0xe2, 0xe2, 0, 0, 0xd3, 0, 0, 0, 0, 0, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y -SCB accu_lind8[] = { 0, 0, 0x07, 0, 0, 0x12, 0, 0, 0x27, 0, 0, 0x32, 0, 0, 0x47, 0, 0, 0x52, 0, 0, 0x67, 0, 0, 0x72, 0, 0, 0x87, 0, 0, 0x92, 0, 0, 0xa7, 0, 0, 0xb2, 0, 0, 0xc7, 0, 0, 0xd2, 0, 0, 0xe7, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff] +SCB accu_sindy8[] = { 0, 0, 0x13, 0, 0, 0, 0, 0, 0x33, 0, 0, 0, 0, 0, 0x53, 0, 0, 0, 0, 0, 0x73, 0, 0, 0, 0, 0, 0x93, 0x82, 0x82, 0, 0, 0, 0xb3, 0xe2, 0xe2, 0, 0, 0, 0xd3, 0, 0, 0, 0, 0, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y +SCB accu_lind8[] = { 0, 0, 0x07, 0, 0, 0x12, 0, 0, 0x27, 0, 0, 0x32, 0, 0, 0x47, 0, 0, 0x52, 0, 0, 0x67, 0, 0, 0x72, 0, 0, 0x87, 0, 0, 0x92, 0, 0, 0xa7, 0, 0, 0, 0, 0, 0xc7, 0, 0, 0xd2, 0, 0, 0xe7, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff] SCB accu_lindy8[] = { 0, 0, 0x17, 0, 0, 0, 0, 0, 0x37, 0, 0, 0, 0, 0, 0x57, 0, 0, 0, 0, 0, 0x77, 0, 0, 0, 0, 0, 0x97, 0, 0, 0, 0, 0, 0xb7, 0, 0, 0, 0, 0, 0xd7, 0, 0, 0, 0, 0, 0xf7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],y -SCB accu_indz8[] = { 0, 0, 0, 0x12, 0x12, 0, 0, 0, 0, 0x32, 0x32, 0, 0, 0, 0, 0x52, 0x52, 0, 0, 0, 0, 0x72, 0x72, 0, 0, 0, 0, 0x92, 0x92, 0, 0, 0, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0, 0, 0xf2, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff),z -SCB accu_lindz8[] = { 0, 0, 0, 0, 0x12, 0, 0, 0, 0, 0, 0x32, 0, 0, 0, 0, 0, 0x52, 0, 0, 0, 0, 0, 0x72, 0, 0, 0, 0, 0, 0x92, 0, 0, 0, 0, 0, 0xb2, 0, 0, 0, 0, 0, 0xd2, 0, 0, 0, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],z (encoded as a NOP plus ($ff),z) +SCB accu_indz8[] = { 0, 0, 0, 0x12, 0x12, 0, 0, 0, 0, 0x32, 0x32, 0, 0, 0, 0, 0x52, 0x52, 0, 0, 0, 0, 0x72, 0x72, 0, 0, 0, 0, 0x92, 0x92, 0, 0, 0, 0, 0xb2, 0xb2, 0xb2, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0, 0, 0xf2, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff),z +SCB accu_lindz8[] = { 0, 0, 0, 0, 0x12, 0, 0, 0, 0, 0, 0x32, 0, 0, 0, 0, 0, 0x52, 0, 0, 0, 0, 0, 0x72, 0, 0, 0, 0, 0, 0x92, 0, 0, 0, 0, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0, 0, 0, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],z (encoded as a NOP plus ($ff),z) // Code tables for group GROUP_MISC: // These tables are needed for finding out the correct code in cases when diff --git a/src/version.h b/src/version.h index 9b7da31..dcd6a85 100644 --- a/src/version.h +++ b/src/version.h @@ -9,8 +9,8 @@ #define RELEASE "0.97" // update before release FIXME #define CODENAME "Zem" // update before release -#define CHANGE_DATE "23 Nov" // update before release FIXME -#define CHANGE_YEAR "2024" // update before release +#define CHANGE_DATE "4 May" // update before release FIXME +#define CHANGE_YEAR "2025" // update before release //#define HOME_PAGE "http://home.pages.de/~mac_bacon/smorbrod/acme/" #define HOME_PAGE "http://sourceforge.net/p/acme-crossass/" // FIXME diff --git a/testing/cpus/out-m65.exp b/testing/cpus/out-m65.exp index 9e4e715d49aff4db0780831a6257323b62e8e68f..772db10e5adeae95cb17cf8af07e99331e10e12c 100644 GIT binary patch delta 18 acmey#_LyzMV