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fixed addressing modes for M65 cpu (see tickets 22 and 23)

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git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@436 4df02467-bbd4-4a76-a152-e7ce94205b78
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marcobaye
2025-05-07 11:08:18 +00:00
parent b27022ac4b
commit 8647561ac0
6 changed files with 41 additions and 36 deletions
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19
docs/cputypes/all.txt
View File

@@ -178,7 +178,8 @@ Features:
- "quad mode" (32-bit data operations on virtual register 'Q')
- "long mode" (32-bit pointer addressing for existing mnemonics)
- "quad" and "long" modes can be combined
quad mode introduces several new mnemonics:
"quad" mode introduces several new mnemonics:
LDQ/STQ/CPQ like LDA/STA/CMP
ADCQ/SBCQ like ADC/SBC
ANDQ/EORQ/ORQ like AND/EOR/ORA
@@ -189,10 +190,11 @@ quad mode introduces several new mnemonics:
The new mnemonics support most of the addressing modes of the
original mnemonics with these exceptions:
- there is no immediate addressing
- indirect-Z-indexed addressing becomes indirect addressing
- indirect-Z-indexed addressing becomes indirect addressing,
except for LDQ.
- all other indexed addressing modes can only really be used
with read-modify-write instructions or LDQ, because otherwise
a part of the 'Q' value would be used as the index.
with read-modify-write instructions, because otherwise a part
of the 'Q' value would be used as the index.
CAUTION: The STQ instruction clobbers the N and Z flags!
There is no "real" Q register, instead A/X/Y/Z are combined to form
the Q register (A holds lsb, Z holds msb), except for read-modify-
@@ -200,7 +202,8 @@ quad mode introduces several new mnemonics:
using A/X/Y/Z.
To load a 32-bit immediate constant into the Q register, use the
+movq macro from the <m65/std.a> library file.
long mode brings a single new addressing mode for eight mnemonics:
"long" mode brings a single new addressing mode for eight mnemonics:
LDA [$12], z contents of $12/$13/$14/$15
STA [$12], z plus z form the address
CMP [$12], z
@@ -209,9 +212,10 @@ long mode brings a single new addressing mode for eight mnemonics:
AND [$12], z
EOR [$12], z
ORA [$12], z
quad and long modes combined result in another addressing mode for
"quad" and "long" modes combined result in another addressing mode for
eight of the new mnemonics:
LDQ [$12] contents of $12/$13/$14/$15
LDQ [$12], z contents of $12/$13/$14/$15
STQ [$12] form the address
CPQ [$12]
ADCQ [$12]
@@ -219,6 +223,7 @@ quad and long modes combined result in another addressing mode for
ANDQ [$12]
EORQ [$12]
ORQ [$12]
The NOP mnemonic is disabled for this instruction set because its
opcode is re-used internally as a prefix byte.
CAUTION: The !align pseudo opcode still inserts NOPs.

24
docs/cputypes/cpu m65.txt
View File

@@ -8,10 +8,8 @@ file), so this file only contains information about the extensions.
"quad mode" allows 32-bit data operations using a virtual register called 'Q'.
The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes.
The mnemonic ldq has eight addressing modes in quad mode, and a ninth when
combined with long mode.
The mnemonics stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes in
quad mode, and a fourth when combined with long mode.
The mnemonics ldq/stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes
in quad mode, and a fourth when combined with long mode.
The mnemonic bitq has two addressing modes.
The mnemonic asrq has three addressing modes.
This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
@@ -66,10 +64,10 @@ a0 a1 a2 a3
a4 a5 ldq zp a6 a7
a8 a9 aa ab
ac ad ldq abs16 ae af
b0 b1 ldq (zp), y b2 ldq (zp) b3
b4 b5 ldq zp, x b6 b7
b8 b9 ldq abs16, y ba bb
bc bd ldq abs16, x be bf
b0 b1 b2 ldq (zp), z b3
b4 b5 b6 b7
b8 b9 ba bb
bc bd be bf
c0 c1 c2 c3
c4 c5 cpq zp c6 deq zp c7
@@ -80,7 +78,7 @@ d4 d5 d6 deq zp, x d7
d8 d9 da db
dc dd de deq abs16, x df
e0 e1 e2 ldq (zp, s), y e3
e0 e1 e2 e3
e4 e5 sbcq zp e6 inq zp e7
e8 e9 ea eb
ec ed sbcq abs16 ee inq abs16 ef
@@ -107,7 +105,7 @@ mnemonics. This mode is entered after a NEG:NEG:NOP (42 42 ea) prefix, the
following opcode should then be one of these:
12 orq [zp] 32 andq [zp] 52 eorq [zp] 72 adcq [zp]
92 stq [zp] b2 ldq [zp] d2 cpq [zp] f2 sbcq [zp]
92 stq [zp] b2 ldq [zp], z d2 cpq [zp] f2 sbcq [zp]
Because the addressing modes are changed a bit by the prefix codes, here are
@@ -116,5 +114,7 @@ some of the unsupported combinations just for comparison (these result in
lda (zp) ; 65c02 knew this, but 65ce02 added z index!
lda [zp] ; long mode also expects z index!
ldq #imm ; quad mode has no immediate addressing!
ldq (zp), z ; quad mode does not use z index!
ldq [zp], z ; quad and long modes combined do not use z index!
stq (zp), z ; quad mode only uses z index for LDQ!
stq [zp], z ; quad+long mode only uses z index for LDQ!
ldq (zp) ; LDQ uses z index!
ldq [zp] ; LDQ in long mode uses z index!