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cleaned up list of cpu types and added opcode table(s) for m65 cpu

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git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@272 4df02467-bbd4-4a76-a152-e7ce94205b78
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marcobaye 2020-06-29 15:10:42 +00:00
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171
docs/cputypes/all.txt
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@ -7,11 +7,32 @@
--- cpu types ---
ACME supports the following cpu types:
ACME supports the following cpu types (shown here as a sort of family
tree):
6502 standard
|
|\_nmos6502 (=6510) + undocumented opcodes
|
|\_c64dtv2 + BRA/SAC/SIR and some (not all!) undocumented
|
\_65c02 + BRA/PHX/PHY/PLX/PLY/STZ/TRB/TSB/...
|
|\_65816 16 bit regs, 24 bit address space, ...
|
\_r65c02 + bit manipulation instructions
|
|\_w65c02 + STP/WAI
|
\_65ce02 + Z reg, long branches, ...
|
\_4502 + MAP/EOM
|
\_m65 + 32-bit pointers, 32-bit 'Q' register
*** 6502
!cpu 6502
This is the official instruction set of the original NMOS 6502 CPU
designed by MOS (later CSG).
@ -21,16 +42,34 @@ the mnemonic without any argument: "LSR" will work, "LSR A" won't.
*** 6510
!cpu nmos6502
This is the 6502 variant used in the C64 computer. It uses the same
instruction set as the 6502, but in addition to that, ACME supports
most of the undocumented opcodes as well.
This instruction set includes the undocumented ("illegal") opcodes of
the NMOS 6502.
See "docs/Illegals.txt" for more info.
*** 65c02
!cpu 6510
This is an alias for "nmos6502", because the 6510 cpu (as used in the
C64 computer) is a variant of this type.
!cpu c64dtv2
This is the cpu in version 2 of the C64DTV. It uses a superset of the
6502 instruction set. Features:
- new instructions:
BRA near_target branch always
SAC #$12 set accumulator mapping
SIR #$12 set index register mapping
- support for some (but not all!) of the undocumented opcodes.
!cpu 65c02
This is the CMOS re-design of the 6502. It seems to have also been
available from Rockwell, GTE/CMD and others. Features:
@ -61,7 +100,21 @@ There are 178 documented opcodes.
*** r65c02
!cpu 65816
This is a superset of 65c02, originally designed by WDC (it seems to
have been available from GTE/CMD as well). Features:
- register sizes can be changed to 16-bit
- 24-bit address space
- several new instructions (including block transfers)
- several new addressing modes for existing instructions
There are 256 documented opcodes, but one of them ("WDM") is reserved
for future expansion.
See "docs/65816.txt" for more info.
!cpu r65c02
This is a superset of 65c02, probably originally by Rockwell. It adds
bit manipulation instructions:
@ -77,7 +130,7 @@ There are 210 documented opcodes.
*** w65c02
!cpu w65c02
This is a superset of r65c02, originating at WDC. It adds two new
instructions:
@ -87,21 +140,7 @@ There are 212 documented opcodes.
*** 65816
This is a superset of 65c02, originally designed by WDC (it seems to
have been available from GTE/CMD as well). Features:
- register sizes can be changed to 16-bit
- 24-bit address space
- several new instructions (including block transfers)
- several new addressing modes for existing instructions
There are 256 documented opcodes, but one of them ("WDM") is reserved
for future expansion.
See "docs/65816.txt" for more info.
*** 65ce02
!cpu 65ce02
This is a superset of r65c02, originating at CSG. Features:
- Z register
@ -121,7 +160,7 @@ unconditional") instead. ACME accepts both mnemonics.
*** 4502
!cpu 4502
This is basically the same as 65ce02, but
- MAP replaces AUG
@ -131,65 +170,51 @@ There are 256 documented opcodes.
*** m65
!cpu m65
This is a superset of 4502 specified by the MEGA65 project. It uses
NOP and NEG:NEG as prefix bytes to extend the instruction set.
NEG:NEG and NOP as prefix bytes to extend the instruction set.
Features:
- new "long indirect z-indexed" addressing mode with four-byte-pointer
for existing instructions:
LDA/STA/ADC/SBC [$12], z ; contents of $12/$13/$14/$15
AND/ORA/EOR/CMP [$12], z ; plus z form the address
- 32-bit data operations indicated via 'Q' ("quad"):
- "quad mode" (32-bit data operations on virtual register 'Q')
- "long mode" (32-bit pointer addressing for existing mnemonics)
- "quad" and "long" modes can be combined
quad mode introduces several new mnemonics:
LDQ/STQ/CPQ like LDA/STA/CMP
ADCQ/SBCQ like ADC/SBC
ANDQ/EORQ/ORQ like AND/EOR/ORA
ASLQ/LSRQ/ROLQ/RORQ like ASL/LSR/ROL/ROR
INQ/DEQ like INC/DEC
The new mnemonics support all the addressing modes of the original
mnemonics, except there are no 32-bit immediate arguments.
CAUTION: The STQ mnemonic clobbers the N and Z flags!
mnemonics with two exceptions:
- there are no 32-bit immediate arguments
- indirect-z addressing becomes indirect addressing
CAUTION: The STQ instruction clobbers the N and Z flags!
There is no "real" Q register, instead A/X/Y/Z are combined to form
the Q register (A holds lsb, Z holds msb), except for read-modify-
write instructions, where the 32-bit operation is performed without
using A/X/Y/Z.
- The NOP mnemonic is disabled for this instruction set because its
opcode is re-used internally as a prefix byte.
CAUTION: The !align pseudo opcode still inserts NOPs.
To load a 32-bit immediate constant into the Q register, use the
+movq macro from the <m65/std.a> library file.
long mode brings a single new addressing mode for eight mnemonics:
LDA [$12], z contents of $12/$13/$14/$15
STA [$12], z plus z form the address
CMP [$12], z
ADC [$12], z
SBC [$12], z
AND [$12], z
EOR [$12], z
ORA [$12], z
quad and long modes combined result in another addressing mode for
eight of the new mnemonics:
LDQ [$12] contents of $12/$13/$14/$15
STQ [$12] form the address
CPQ [$12]
ADCQ [$12]
SBCQ [$12]
ANDQ [$12]
EORQ [$12]
ORQ [$12]
The NOP mnemonic is disabled for this instruction set because its
opcode is re-used internally as a prefix byte.
CAUTION: The !align pseudo opcode still inserts NOPs.
*** c64dtv2
This is the cpu in version 2 of the C64DTV. It uses a superset of the
6502 instruction set. Features:
- new instructions:
BRA near_target branch always
SAC #$12 set accumulator mapping
SIR #$12 set index register mapping
- support for some of the undocumented opcodes.
Here's a family tree:
6502 (standard)
|
|\_6510 (+ undocumented opcodes of nmos6502)
|
|\_c64dtv2 (+ bra/sac/sir and some undocumented)
|
\_65c02 (+ bra/phx/phy/plx/ply/stz/trb/tsb, ...)
|
|\_65816 (16 bit regs, 24 bit address space, ...)
|
\_r65c02 (+ bit manipulation instructions)
|
|\_w65c02 (+ stp/wai)
|
\_65ce02 (+ Z reg, long branches, ...)
|
\_4502 (+ map/eom)
|
\_m65 (+ 32-bit pointers, 32-bit data)

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@ -0,0 +1,118 @@
m65 opcode table(s)
The m65 instruction set extends the 4502 instruction set using prefix bytes.
Therefore, the "normal" opcode table is the same as for the 4502 cpu (see that
file), so this file only contains information about the extensions.
"quad mode" allows 32-bit data operations using a virtual register called 'Q'.
The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes in quad
mode.
The mnemonics ldq/stq have nine addressing modes in quad mode.
The mnemonics cpq/adcq/sbcq/andq/eorq/orq have eight addressing modes in quad
mode.
This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
then taken from this table:
00 01 orq (zp, x) 02 03
04 05 orq zp 06 aslq zp 07
08 09 0a aslq 0b
0c 0d orq abs16 0e aslq abs16 0f
10 11 orq (zp), y 12 orq (zp) 13
14 15 orq zp, x 16 aslq zp, x 17
18 19 orq abs16, y 1a inq 1b
1c 1d orq abs16, x 1e aslq abs16, x 1f
20 21 andq (zp, x) 22 23
24 25 andq zp 26 rolq zp 27
28 29 2a rolq 2b
2c 2d andq abs16 2e rolq abs16 2f
30 31 andq (zp), y 32 andq (zp) 33
34 35 andq zp, x 36 rolq zp, x 37
38 39 andq abs16, y 3a deq 3b
3c 3d andq abs16, x 3e rolq abs16, x 3f
40 41 eorq (zp, x) 42 43
44 45 eorq zp 46 lsrq zp 47
48 49 4a lsrq 4b
4c 4d eorq abs16 4e lsrq abs16 4f
50 51 eorq (zp), y 52 eorq (zp) 53
54 55 eorq zp, x 56 lsrq zp, x 57
58 59 eorq abs16, y 5a 5b
5c 5d eorq abs16, x 5e lsrq abs16, x 5f
60 61 adcq (zp, x) 62 63
64 65 adcq zp 66 rorq zp 67
68 69 6a rorq 6b
6c 6d adcq abs16 6e rorq abs16 6f
70 71 adcq (zp), y 72 adcq (zp) 73
74 75 adcq zp, x 76 rorq zp, x 77
78 79 adcq abs16, y 7a 7b
7c 7d adcq abs16, x 7e rorq abs16, x 7f
80 81 stq (zp, x) 82 stq (zp, s), y 83
84 85 stq zp 86 87
88 89 8a 8b
8c 8d stq abs16 8e 8f
90 91 stq (zp), y 92 stq (zp) 93
94 95 stq zp, x 96 97
98 99 stq abs16, y 9a 9b
9c 9d stq abs16, x 9e 9f
a0 a1 ldq (zp, x) a2 a3
a4 a5 ldq zp a6 a7
a8 a9 aa ab
ac ad ldq abs16 ae af
b0 b1 ldq (zp), y b2 ldq (zp) b3
b4 b5 ldq zp, x b6 b7
b8 b9 ldq abs16, y ba bb
bc bd ldq abs16, x be bf
c0 c1 cpq (zp, x) c2 c3
c4 c5 cpq zp c6 deq zp c7
c8 c9 ca cb
cc cd cpq abs16 ce deq abs16 cf
d0 d1 cpq (zp), y d2 cpq (zp) d3
d4 d5 cpq zp, x d6 deq zp, x d7
d8 d9 cpq abs16, y da db
dc dd cpq abs16, x de deq abs16, x df
e0 e1 sbcq (zp, x) e2 ldq (zp, s), y e3
e4 e5 sbcq zp e6 inq zp e7
e8 e9 ea eb
ec ed sbcq abs16 ee inq abs16 ef
f0 f1 sbcq (zp), y f2 sbcq (zp) f3
f4 f5 sbcq zp, x f6 inq zp, x f7
f8 f9 sbcq abs16, y fa fb
fc fd sbcq abs16, x fe inq abs16, x ff
zp: 8-bit zeropage address
abs16: 16-bit absolute address
"long mode" adds an addressing mode using 32-bit pointers for eight existing
mnemonics. This mode is entered after a NOP (ea) prefix, the following opcode
should then be one of these:
12 ora [zp], z 32 and [zp], z 52 eor [zp], z 72 adc [zp], z
92 sta [zp], z b2 lda [zp], z d2 cmp [zp], z f2 sbc [zp], z
"quad" and "long" modes can be combined to have 32-bit data access using a
32-bit pointer. This adds another addressing mode for eight of the new
mnemonics. This mode is entered after a NEG:NEG:NOP (42 42 ea) prefix, the
following opcode should then be one of these:
12 orq [zp] 32 andq [zp] 52 eorq [zp] 72 adcq [zp]
92 stq [zp] b2 ldq [zp] d2 cpq [zp] f2 sbcq [zp]
Because the addressing modes are changed a bit by the prefix codes, here are
some of the unsupported combinations just for comparison (these result in
"Illegal combination of command and addressing mode"):
lda (zp) ; 65c02 knew this, but 65ce02 added z index!
lda [zp] ; long mode also expects z index!
ldq #imm ; quad mode has no immediate addressing!
ldq (zp), z ; quad mode does not use z index!
ldq [zp], z ; quad and long modes combined do not use z index!