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cleaned up list of cpu types and added opcode table(s) for m65 cpu
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@272 4df02467-bbd4-4a76-a152-e7ce94205b78
This commit is contained in:
marcobaye
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@ -7,11 +7,32 @@
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--- cpu types ---
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--- cpu types ---
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ACME supports the following cpu types:
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ACME supports the following cpu types (shown here as a sort of family
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tree):
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6502 standard
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|\_nmos6502 (=6510) + undocumented opcodes
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|\_c64dtv2 + BRA/SAC/SIR and some (not all!) undocumented
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\_65c02 + BRA/PHX/PHY/PLX/PLY/STZ/TRB/TSB/...
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|\_65816 16 bit regs, 24 bit address space, ...
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\_r65c02 + bit manipulation instructions
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|\_w65c02 + STP/WAI
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\_65ce02 + Z reg, long branches, ...
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\_4502 + MAP/EOM
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\_m65 + 32-bit pointers, 32-bit 'Q' register
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*** 6502
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!cpu 6502
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This is the official instruction set of the original NMOS 6502 CPU
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This is the official instruction set of the original NMOS 6502 CPU
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designed by MOS (later CSG).
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designed by MOS (later CSG).
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@ -21,16 +42,34 @@ the mnemonic without any argument: "LSR" will work, "LSR A" won't.
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*** 6510
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!cpu nmos6502
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This is the 6502 variant used in the C64 computer. It uses the same
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This instruction set includes the undocumented ("illegal") opcodes of
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instruction set as the 6502, but in addition to that, ACME supports
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the NMOS 6502.
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most of the undocumented opcodes as well.
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See "docs/Illegals.txt" for more info.
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See "docs/Illegals.txt" for more info.
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*** 65c02
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!cpu 6510
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This is an alias for "nmos6502", because the 6510 cpu (as used in the
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C64 computer) is a variant of this type.
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!cpu c64dtv2
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This is the cpu in version 2 of the C64DTV. It uses a superset of the
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6502 instruction set. Features:
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- new instructions:
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BRA near_target branch always
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SAC #$12 set accumulator mapping
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SIR #$12 set index register mapping
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- support for some (but not all!) of the undocumented opcodes.
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!cpu 65c02
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This is the CMOS re-design of the 6502. It seems to have also been
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This is the CMOS re-design of the 6502. It seems to have also been
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available from Rockwell, GTE/CMD and others. Features:
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available from Rockwell, GTE/CMD and others. Features:
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@ -61,7 +100,21 @@ There are 178 documented opcodes.
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*** r65c02
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!cpu 65816
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This is a superset of 65c02, originally designed by WDC (it seems to
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have been available from GTE/CMD as well). Features:
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- register sizes can be changed to 16-bit
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- 24-bit address space
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- several new instructions (including block transfers)
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- several new addressing modes for existing instructions
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There are 256 documented opcodes, but one of them ("WDM") is reserved
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for future expansion.
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See "docs/65816.txt" for more info.
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!cpu r65c02
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This is a superset of 65c02, probably originally by Rockwell. It adds
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This is a superset of 65c02, probably originally by Rockwell. It adds
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bit manipulation instructions:
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bit manipulation instructions:
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@ -77,7 +130,7 @@ There are 210 documented opcodes.
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*** w65c02
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!cpu w65c02
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This is a superset of r65c02, originating at WDC. It adds two new
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This is a superset of r65c02, originating at WDC. It adds two new
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instructions:
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instructions:
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@ -87,21 +140,7 @@ There are 212 documented opcodes.
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*** 65816
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!cpu 65ce02
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This is a superset of 65c02, originally designed by WDC (it seems to
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have been available from GTE/CMD as well). Features:
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- register sizes can be changed to 16-bit
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- 24-bit address space
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- several new instructions (including block transfers)
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- several new addressing modes for existing instructions
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There are 256 documented opcodes, but one of them ("WDM") is reserved
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for future expansion.
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See "docs/65816.txt" for more info.
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*** 65ce02
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This is a superset of r65c02, originating at CSG. Features:
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This is a superset of r65c02, originating at CSG. Features:
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- Z register
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- Z register
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@ -121,7 +160,7 @@ unconditional") instead. ACME accepts both mnemonics.
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*** 4502
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!cpu 4502
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This is basically the same as 65ce02, but
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This is basically the same as 65ce02, but
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- MAP replaces AUG
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- MAP replaces AUG
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@ -131,65 +170,51 @@ There are 256 documented opcodes.
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*** m65
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!cpu m65
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This is a superset of 4502 specified by the MEGA65 project. It uses
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This is a superset of 4502 specified by the MEGA65 project. It uses
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NOP and NEG:NEG as prefix bytes to extend the instruction set.
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NEG:NEG and NOP as prefix bytes to extend the instruction set.
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Features:
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Features:
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- new "long indirect z-indexed" addressing mode with four-byte-pointer
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- "quad mode" (32-bit data operations on virtual register 'Q')
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for existing instructions:
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- "long mode" (32-bit pointer addressing for existing mnemonics)
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LDA/STA/ADC/SBC [$12], z ; contents of $12/$13/$14/$15
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- "quad" and "long" modes can be combined
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AND/ORA/EOR/CMP [$12], z ; plus z form the address
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quad mode introduces several new mnemonics:
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- 32-bit data operations indicated via 'Q' ("quad"):
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LDQ/STQ/CPQ like LDA/STA/CMP
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LDQ/STQ/CPQ like LDA/STA/CMP
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ADCQ/SBCQ like ADC/SBC
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ADCQ/SBCQ like ADC/SBC
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ANDQ/EORQ/ORQ like AND/EOR/ORA
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ANDQ/EORQ/ORQ like AND/EOR/ORA
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ASLQ/LSRQ/ROLQ/RORQ like ASL/LSR/ROL/ROR
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ASLQ/LSRQ/ROLQ/RORQ like ASL/LSR/ROL/ROR
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INQ/DEQ like INC/DEC
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INQ/DEQ like INC/DEC
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The new mnemonics support all the addressing modes of the original
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The new mnemonics support all the addressing modes of the original
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mnemonics, except there are no 32-bit immediate arguments.
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mnemonics with two exceptions:
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CAUTION: The STQ mnemonic clobbers the N and Z flags!
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- there are no 32-bit immediate arguments
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- indirect-z addressing becomes indirect addressing
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CAUTION: The STQ instruction clobbers the N and Z flags!
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There is no "real" Q register, instead A/X/Y/Z are combined to form
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There is no "real" Q register, instead A/X/Y/Z are combined to form
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the Q register (A holds lsb, Z holds msb), except for read-modify-
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the Q register (A holds lsb, Z holds msb), except for read-modify-
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write instructions, where the 32-bit operation is performed without
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write instructions, where the 32-bit operation is performed without
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using A/X/Y/Z.
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using A/X/Y/Z.
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- The NOP mnemonic is disabled for this instruction set because its
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To load a 32-bit immediate constant into the Q register, use the
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opcode is re-used internally as a prefix byte.
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+movq macro from the <m65/std.a> library file.
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CAUTION: The !align pseudo opcode still inserts NOPs.
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long mode brings a single new addressing mode for eight mnemonics:
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LDA [$12], z contents of $12/$13/$14/$15
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STA [$12], z plus z form the address
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CMP [$12], z
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ADC [$12], z
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SBC [$12], z
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AND [$12], z
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EOR [$12], z
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ORA [$12], z
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quad and long modes combined result in another addressing mode for
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eight of the new mnemonics:
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LDQ [$12] contents of $12/$13/$14/$15
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STQ [$12] form the address
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CPQ [$12]
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ADCQ [$12]
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SBCQ [$12]
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ANDQ [$12]
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EORQ [$12]
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ORQ [$12]
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The NOP mnemonic is disabled for this instruction set because its
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opcode is re-used internally as a prefix byte.
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CAUTION: The !align pseudo opcode still inserts NOPs.
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*** c64dtv2
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This is the cpu in version 2 of the C64DTV. It uses a superset of the
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6502 instruction set. Features:
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- new instructions:
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BRA near_target branch always
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SAC #$12 set accumulator mapping
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SIR #$12 set index register mapping
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- support for some of the undocumented opcodes.
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Here's a family tree:
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6502 (standard)
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|\_6510 (+ undocumented opcodes of nmos6502)
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|\_c64dtv2 (+ bra/sac/sir and some undocumented)
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\_65c02 (+ bra/phx/phy/plx/ply/stz/trb/tsb, ...)
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|\_65816 (16 bit regs, 24 bit address space, ...)
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\_r65c02 (+ bit manipulation instructions)
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|\_w65c02 (+ stp/wai)
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\_65ce02 (+ Z reg, long branches, ...)
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\_4502 (+ map/eom)
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\_m65 (+ 32-bit pointers, 32-bit data)
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118
docs/cputypes/cpu m65.txt
Normal file
118
docs/cputypes/cpu m65.txt
Normal file
@ -0,0 +1,118 @@
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m65 opcode table(s)
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The m65 instruction set extends the 4502 instruction set using prefix bytes.
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Therefore, the "normal" opcode table is the same as for the 4502 cpu (see that
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file), so this file only contains information about the extensions.
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"quad mode" allows 32-bit data operations using a virtual register called 'Q'.
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The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes in quad
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mode.
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The mnemonics ldq/stq have nine addressing modes in quad mode.
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The mnemonics cpq/adcq/sbcq/andq/eorq/orq have eight addressing modes in quad
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mode.
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This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
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then taken from this table:
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00 01 orq (zp, x) 02 03
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04 05 orq zp 06 aslq zp 07
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08 09 0a aslq 0b
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0c 0d orq abs16 0e aslq abs16 0f
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10 11 orq (zp), y 12 orq (zp) 13
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14 15 orq zp, x 16 aslq zp, x 17
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18 19 orq abs16, y 1a inq 1b
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1c 1d orq abs16, x 1e aslq abs16, x 1f
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20 21 andq (zp, x) 22 23
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24 25 andq zp 26 rolq zp 27
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28 29 2a rolq 2b
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2c 2d andq abs16 2e rolq abs16 2f
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30 31 andq (zp), y 32 andq (zp) 33
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34 35 andq zp, x 36 rolq zp, x 37
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38 39 andq abs16, y 3a deq 3b
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3c 3d andq abs16, x 3e rolq abs16, x 3f
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40 41 eorq (zp, x) 42 43
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44 45 eorq zp 46 lsrq zp 47
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48 49 4a lsrq 4b
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4c 4d eorq abs16 4e lsrq abs16 4f
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50 51 eorq (zp), y 52 eorq (zp) 53
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54 55 eorq zp, x 56 lsrq zp, x 57
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58 59 eorq abs16, y 5a 5b
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5c 5d eorq abs16, x 5e lsrq abs16, x 5f
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60 61 adcq (zp, x) 62 63
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64 65 adcq zp 66 rorq zp 67
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68 69 6a rorq 6b
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6c 6d adcq abs16 6e rorq abs16 6f
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70 71 adcq (zp), y 72 adcq (zp) 73
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74 75 adcq zp, x 76 rorq zp, x 77
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78 79 adcq abs16, y 7a 7b
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7c 7d adcq abs16, x 7e rorq abs16, x 7f
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80 81 stq (zp, x) 82 stq (zp, s), y 83
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84 85 stq zp 86 87
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88 89 8a 8b
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8c 8d stq abs16 8e 8f
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90 91 stq (zp), y 92 stq (zp) 93
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94 95 stq zp, x 96 97
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98 99 stq abs16, y 9a 9b
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9c 9d stq abs16, x 9e 9f
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a0 a1 ldq (zp, x) a2 a3
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a4 a5 ldq zp a6 a7
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a8 a9 aa ab
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ac ad ldq abs16 ae af
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b0 b1 ldq (zp), y b2 ldq (zp) b3
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b4 b5 ldq zp, x b6 b7
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b8 b9 ldq abs16, y ba bb
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bc bd ldq abs16, x be bf
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c0 c1 cpq (zp, x) c2 c3
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c4 c5 cpq zp c6 deq zp c7
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c8 c9 ca cb
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cc cd cpq abs16 ce deq abs16 cf
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d0 d1 cpq (zp), y d2 cpq (zp) d3
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d4 d5 cpq zp, x d6 deq zp, x d7
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d8 d9 cpq abs16, y da db
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dc dd cpq abs16, x de deq abs16, x df
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e0 e1 sbcq (zp, x) e2 ldq (zp, s), y e3
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e4 e5 sbcq zp e6 inq zp e7
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e8 e9 ea eb
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ec ed sbcq abs16 ee inq abs16 ef
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f0 f1 sbcq (zp), y f2 sbcq (zp) f3
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f4 f5 sbcq zp, x f6 inq zp, x f7
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f8 f9 sbcq abs16, y fa fb
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fc fd sbcq abs16, x fe inq abs16, x ff
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zp: 8-bit zeropage address
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abs16: 16-bit absolute address
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"long mode" adds an addressing mode using 32-bit pointers for eight existing
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mnemonics. This mode is entered after a NOP (ea) prefix, the following opcode
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should then be one of these:
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12 ora [zp], z 32 and [zp], z 52 eor [zp], z 72 adc [zp], z
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92 sta [zp], z b2 lda [zp], z d2 cmp [zp], z f2 sbc [zp], z
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"quad" and "long" modes can be combined to have 32-bit data access using a
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32-bit pointer. This adds another addressing mode for eight of the new
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mnemonics. This mode is entered after a NEG:NEG:NOP (42 42 ea) prefix, the
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following opcode should then be one of these:
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12 orq [zp] 32 andq [zp] 52 eorq [zp] 72 adcq [zp]
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92 stq [zp] b2 ldq [zp] d2 cpq [zp] f2 sbcq [zp]
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Because the addressing modes are changed a bit by the prefix codes, here are
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some of the unsupported combinations just for comparison (these result in
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"Illegal combination of command and addressing mode"):
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lda (zp) ; 65c02 knew this, but 65ce02 added z index!
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lda [zp] ; long mode also expects z index!
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ldq #imm ; quad mode has no immediate addressing!
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ldq (zp), z ; quad mode does not use z index!
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ldq [zp], z ; quad and long modes combined do not use z index!
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