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disabled all indexed addressing for m65's "quad" mode, except for LDQ.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@287 4df02467-bbd4-4a76-a152-e7ce94205b78
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marcobaye
@@ -186,13 +186,13 @@ quad mode introduces several new mnemonics:
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INQ/DEQ like INC/DEC
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BITQ like BIT
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ASRQ like ASR
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The new mnemonics support all the addressing modes of the original
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mnemonics with these exceptions:
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The new mnemonics support most of the addressing modes of the
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original mnemonics with these exceptions:
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- there is no immediate addressing
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- indirect-Z-indexed addressing becomes indirect addressing
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- all other indexed addressing modes are only really useful
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- all other indexed addressing modes can only really be used
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with read-modify-write instructions or LDQ, because otherwise
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a part of the 'Q' value will be used as the index.
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a part of the 'Q' value would be used as the index.
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CAUTION: The STQ instruction clobbers the N and Z flags!
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There is no "real" Q register, instead A/X/Y/Z are combined to form
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the Q register (A holds lsb, Z holds msb), except for read-modify-
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@@ -8,61 +8,61 @@ file), so this file only contains information about the extensions.
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"quad mode" allows 32-bit data operations using a virtual register called 'Q'.
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The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes.
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The mnemonics ldq/stq have nine addressing modes in quad mode, and a tenth
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when combined with long mode.
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The mnemonics cpq/adcq/sbcq/andq/eorq/orq have eight addressing modes in quad
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mode, and a ninth when combined with long mode.
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The mnemonic bitq has four addressing modes.
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The mnemonic ldq has eight addressing modes in quad mode, and a ninth when
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combined with long mode.
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The mnemonics stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes in
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quad mode, and a fourth when combined with long mode.
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The mnemonic bitq has two addressing modes.
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The mnemonic asrq has three addressing modes.
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This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
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then taken from this table:
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00 01 orq (zp, x) 02 03
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00 01 02 03
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04 05 orq zp 06 aslq zp 07
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08 09 0a aslq 0b
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0c 0d orq abs16 0e aslq abs16 0f
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10 11 orq (zp), y 12 orq (zp) 13
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14 15 orq zp, x 16 aslq zp, x 17
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18 19 orq abs16, y 1a inq 1b
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1c 1d orq abs16, x 1e aslq abs16, x 1f
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10 11 12 orq (zp) 13
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14 15 16 aslq zp, x 17
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18 19 1a inq 1b
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1c 1d 1e aslq abs16, x 1f
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20 21 andq (zp, x) 22 23
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20 21 22 23
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24 bitq zp 25 andq zp 26 rolq zp 27
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28 29 2a rolq 2b
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2c bitq abs16 2d andq abs16 2e rolq abs16 2f
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30 31 andq (zp), y 32 andq (zp) 33
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34 bitq zp, x 35 andq zp, x 36 rolq zp, x 37
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38 39 andq abs16, y 3a deq 3b
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3c bitq abs16, x 3d andq abs16, x 3e rolq abs16, x 3f
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30 31 32 andq (zp) 33
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34 35 36 rolq zp, x 37
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38 39 3a deq 3b
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3c 3d 3e rolq abs16, x 3f
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40 41 eorq (zp, x) 42 43 asrq
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40 41 42 43 asrq
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44 asrq zp 45 eorq zp 46 lsrq zp 47
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48 49 4a lsrq 4b
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4c 4d eorq abs16 4e lsrq abs16 4f
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50 51 eorq (zp), y 52 eorq (zp) 53
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54 asrq zp, x 55 eorq zp, x 56 lsrq zp, x 57
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58 59 eorq abs16, y 5a 5b
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5c 5d eorq abs16, x 5e lsrq abs16, x 5f
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50 51 52 eorq (zp) 53
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54 asrq zp, x 55 56 lsrq zp, x 57
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58 59 5a 5b
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5c 5d 5e lsrq abs16, x 5f
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60 61 adcq (zp, x) 62 63
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60 61 62 63
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64 65 adcq zp 66 rorq zp 67
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68 69 6a rorq 6b
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6c 6d adcq abs16 6e rorq abs16 6f
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70 71 adcq (zp), y 72 adcq (zp) 73
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74 75 adcq zp, x 76 rorq zp, x 77
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78 79 adcq abs16, y 7a 7b
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7c 7d adcq abs16, x 7e rorq abs16, x 7f
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70 71 72 adcq (zp) 73
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74 75 76 rorq zp, x 77
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78 79 7a 7b
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7c 7d 7e rorq abs16, x 7f
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80 81 stq (zp, x) 82 stq (zp, s), y 83
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80 81 82 83
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84 85 stq zp 86 87
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88 89 8a 8b
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8c 8d stq abs16 8e 8f
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90 91 stq (zp), y 92 stq (zp) 93
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94 95 stq zp, x 96 97
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98 99 stq abs16, y 9a 9b
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9c 9d stq abs16, x 9e 9f
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90 91 92 stq (zp) 93
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94 95 96 97
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98 99 9a 9b
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9c 9d 9e 9f
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a0 a1 ldq (zp, x) a2 a3
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a0 a1 a2 a3
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a4 a5 ldq zp a6 a7
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a8 a9 aa ab
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ac ad ldq abs16 ae af
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@@ -71,23 +71,23 @@ b4 b5 ldq zp, x b6 b7
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b8 b9 ldq abs16, y ba bb
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bc bd ldq abs16, x be bf
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c0 c1 cpq (zp, x) c2 c3
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c0 c1 c2 c3
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c4 c5 cpq zp c6 deq zp c7
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c8 c9 ca cb
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cc cd cpq abs16 ce deq abs16 cf
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d0 d1 cpq (zp), y d2 cpq (zp) d3
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d4 d5 cpq zp, x d6 deq zp, x d7
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d8 d9 cpq abs16, y da db
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dc dd cpq abs16, x de deq abs16, x df
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d0 d1 d2 cpq (zp) d3
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d4 d5 d6 deq zp, x d7
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d8 d9 da db
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dc dd de deq abs16, x df
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e0 e1 sbcq (zp, x) e2 ldq (zp, s), y e3
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e0 e1 e2 ldq (zp, s), y e3
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e4 e5 sbcq zp e6 inq zp e7
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e8 e9 ea eb
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ec ed sbcq abs16 ee inq abs16 ef
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f0 f1 sbcq (zp), y f2 sbcq (zp) f3
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f4 f5 sbcq zp, x f6 inq zp, x f7
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f8 f9 sbcq abs16, y fa fb
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fc fd sbcq abs16, x fe inq abs16, x ff
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f0 f1 f2 sbcq (zp) f3
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f4 f5 f6 inq zp, x f7
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f8 f9 fa fb
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fc fd fe inq abs16, x ff
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zp: 8-bit zeropage address
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abs16: 16-bit absolute address
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