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Release 0.95.4: Added the last remaining undocumented ("illegal") opcodes: LAS, TAS, SHA, SHX, SHY and ANE.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@44 4df02467-bbd4-4a76-a152-e7ce94205b78
This commit is contained in:
marcobaye
parent
ded7f1a065
commit
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@ -12,6 +12,14 @@ platform used. There should be another help file in this archive
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outlining the platform specific changes.
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----------------------------------------------------------------------
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Section: New in release 0.95.4
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----------------------------------------------------------------------
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Added the last remaining undocumented ("illegal") opcodes: LAS, TAS,
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SHA, SHX, SHY and ANE.
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----------------------------------------------------------------------
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Section: New in release 0.95.3
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----------------------------------------------------------------------
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@ -13,32 +13,42 @@ In release 0.89, some more were added.
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In release 0.94.8, another one was added (lxa).
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In release 0.95.3, C64DTV2 support was added, which includes these
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opcodes as well.
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In release 0.95.4, the remaining seven were added.
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Here are the mnemonics, addressing modes and generated opcodes:
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Here are the new mnemonics, possible addressing modes and generated
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opcodes (mnemonics in parentheses are used by other sources):
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| addressing mode |
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Mnemo | 8 8,x 8,y 16 16,x 16,y (8,x) (8),y | performs:
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------+--------------------------------------------------+-----------
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slo | 07 17 -- 0f 1f 1b 03 13 | asl + ora
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rla | 27 37 -- 2f 3f 3b 23 33 | rol + and
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sre | 47 57 -- 4f 5f 5b 43 53 | lsr + eor
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rra | 67 77 -- 6f 7f 7b 63 73 | ror + adc
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sax | 87 -- 97 8f -- -- 83 -- | stx + sta
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lax | a7 -- b7 af -- bf a3 b3 | ldx + lda
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dcp | c7 d7 -- cf df db c3 d3 | dec + cmp
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isc | e7 f7 -- ef ff fb e3 f3 | inc + sbc
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| addressing mode |
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mnemonic | 8 8,x 8,y 16 16,x 16,y (8,x) (8),y | performs:
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----------------+--------------------------------------+-----------
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slo (aso) | 07 17 0f 1f 1b 03 13 | asl + ora
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rla | 27 37 2f 3f 3b 23 33 | rol + and
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sre (lse) | 47 57 4f 5f 5b 43 53 | lsr + eor
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rra | 67 77 6f 7f 7b 63 73 | ror + adc
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sax (axs, aax) | 87 97 8f 83 | stx + sta
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lax | a7 b7 af bf a3 b3 | ldx + lda
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dcp (dcm) | c7 d7 cf df db c3 d3 | dec + cmp
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isc (isb, ins) | e7 f7 ef ff fb e3 f3 | inc + sbc
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las (lar, lae) | bb | A,X,S = {addr} & S
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These five are said to be unstable:
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tas (shs, xas) | 9b | S = A & X {addr} = A&X& {H+1}
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sha (axa, ahx) | 9f 93 | {addr} = A & X & {H+1}
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shx (xas, sxa) | 9e | {addr} = X & {H+1}
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shy (say, sya) | 9c | {addr} = Y & {H+1}
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| addressing mode |
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Mnemo | implied #8 8 8,x 16 16,x | performs:
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------+-------------------------------------+------------------------
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anc | -- 0b* -- -- -- -- | A = A & arg, then C=N
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asr | -- 4b -- -- -- -- | A = A & arg, then lsr
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arr | -- 6b -- -- -- -- | A = A & arg, then ror
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sbx | -- cb -- -- -- -- | X = (A & X) - arg
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dop | 80** 80 04 14 -- -- | skips next byte
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top | 0c** -- -- -- 0c 1c | skips next two bytes
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jam | 02 -- -- -- -- -- | crash (wait for reset)
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lxa | -- ab*** -- -- -- -- | A/X = (A | ??) & arg
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| addressing mode |
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mnemonic | implied #8 8 8,x 16 16,x | performs:
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----------------+---------------------------------+-----------------------
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anc | 0b* | A = A & arg, then C=N
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asr (alr) | 4b | A = A & arg, then lsr
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arr | 6b | A = A & arg, then ror
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sbx (axs, sax) | cb | X = (A & X) - arg
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dop (nop, skb) | 80** 80 04 14 | skips next byte
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top (nop, skw) | 0c** 0c 1c | skips next two bytes
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jam (kil, hlt) | 02 | crash (wait for reset)
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These two are somewhat unstable, because they involve an arbitrary value:
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ane (xaa) | 8b*** | A = (A | ??) & X & arg
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lxa (lax, atx) | ab*** | A,X = (A | ??) & arg
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Example:
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!cpu 6510 ; activate additional mnemonics...
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@ -49,16 +59,19 @@ Example:
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ACME version 0.95.2, anc#8 generates opcode 0x0b. Both opcodes work
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the same way on a 6510. I am told 0x2b does not work on the C64DTV2.
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**) Note that "dop" and "top" can be used with implied addressing, but
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the generated opcodes are those for immediate and 16-bit absolute
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addressing, respectively. Using dop/top with x-indexed addressing
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might have its uses when timing is critical (crossing a page border
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adds a penalty cycle).
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**) Note that DOP ("double nop") and TOP ("triple nop") can be used
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with implied addressing, but the generated opcodes are those for
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immediate and 16-bit absolute addressing, respectively. Using dop/top
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with x-indexed addressing might have its uses when timing is critical
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(crossing a page border adds a penalty cycle).
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***) This opcode is said to first perform an ORA with an arbitrary(!)
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value, then do an AND with the given argument, then do a TAX.
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This means it is unstable and therefore useless - unless the given
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argument is zero, in which case it reliably clears both A and X.
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***) ANE and LXA first perform an ORA with an arbitrary(!) value and
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then perform an AND with the given argument. So they are unstable and
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therefore useless - unless the given argument is zero:
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ANE #0 reliably clears A - which is still useless; just use LDA #0.
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LXA #0 reliably clears both A and X.
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ACME will output a warning if these opcodes get assembled with a
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nonzero argument.
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There is no guarantee that these opcodes actually work on a given 6502
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(or 6510, or 8500, or 8502) CPU. But as far as I know, nobody ever
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@ -100,15 +113,8 @@ Opcode| Description C64DTV2
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7c | same as 1c and others top 16,x
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82 | same as c2/e2 dop #8, but said to CRASH sometimes
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89 | same as 80 dop #8
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8b | see notes below
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92 | same as 02 and others jam CRASH
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93 | see notes below
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9b | see notes below
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9c | see notes below
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9e | see notes below
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9f | see notes below
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b2 | same as 02 and others jam CRASH
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bb | see notes below
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c2 | same as 82/e2 dop #8, but said to CRASH sometimes
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d2 | same as 02 and others jam CRASH
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d4 | same as 14 and others dop 8,x
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@ -121,22 +127,9 @@ Opcode| Description C64DTV2
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fa | same as (*legal*) ea nop
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fc | same as 1c and others top 16,x
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Concerning opcodes 8b, 93, 9b, 9c, 9e, 9f, bb:
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These opcodes are said to be unstable. For more information about what
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they do, see these documents:
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For more information about what these opcodes do, see these documents:
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John West, Marko Mäkelä. '64doc' file, 1994/06/03.
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Extra Instructions Of The 65XX Series CPU, Adam Vardy, 27 Sept. 1996
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6502 Undocumented Opcodes, by Freddy Offenga, 5/17/1997
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AAY64 (All About Your 64)
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I did not see much point in assigning mnemonics for these opcodes. The
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reference documents above call them:
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8b: ane, xaa
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93: sha, axa, ahx
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9b: shs, tas, xas
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9c: shy, say, sya
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9e: shx, xas, sxa
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9f: sha, axa, ahx
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bb: las, lar, lae
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NMOS 6510 Unintended Opcodes
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@ -15,9 +15,9 @@
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define RELEASE "0.95.3" // update before release (FIXME)
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#define RELEASE "0.95.4" // update before release (FIXME)
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#define CODENAME "Fenchurch" // update before release
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#define CHANGE_DATE "25 Nov" // update before release
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#define CHANGE_DATE "26 Nov" // update before release
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#define CHANGE_YEAR "2014" // update before release
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//#define HOME_PAGE "http://home.pages.de/~mac_bacon/smorbrod/acme/" // FIXME
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#define HOME_PAGE "http://sourceforge.net/p/acme-crossass/" // FIXME
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@ -23,13 +23,13 @@ static struct cpu_type cpu_type_6502 = {
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static struct cpu_type cpu_type_6510 = {
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keyword_is_6510mnemo,
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CPUFLAG_INDIRECTJMPBUGGY | // JMP ($xxFF) is buggy
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CPUFLAG_AB_NEEDS_0_ARG, // LXA #$xx is unstable unless arg is $00
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CPUFLAG_8B_AND_AB_NEED_0_ARG, // ANE/LXA #$xx are unstable unless arg is $00
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234 // !align fills with "NOP"
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};
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static struct cpu_type cpu_type_c64dtv2 = {
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keyword_is_c64dtv2mnemo,
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CPUFLAG_INDIRECTJMPBUGGY | // JMP ($xxFF) is buggy
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CPUFLAG_AB_NEEDS_0_ARG, // LXA #$xx is unstable unless arg is $00 (FIXME - correct?)
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CPUFLAG_8B_AND_AB_NEED_0_ARG, // ANE/LXA #$xx are unstable unless arg is $00 (FIXME - correct?)
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234 // !align fills with "NOP"
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};
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static struct cpu_type cpu_type_65c02 = {
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@ -20,7 +20,7 @@ struct cpu_type {
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};
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#define CPUFLAG_INDIRECTJMPBUGGY (1u << 0) // warn if "jmp ($xxff)" is assembled
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#define CPUFLAG_SUPPORTSLONGREGS (1u << 1) // allow "!al" and "!rl" pseudo opcodes
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#define CPUFLAG_AB_NEEDS_0_ARG (1u << 2) // warn if "lxa #$xx" uses non-zero arg
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#define CPUFLAG_8B_AND_AB_NEED_0_ARG (1u << 2) // warn if "ane/lxa #$xx" uses non-zero arg
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// create cpu type tree (is done early)
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extern void CPUtype_init(void);
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65
src/mnemo.c
65
src/mnemo.c
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@ -89,19 +89,19 @@ enum mnemogroup {
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// column to use here. The row depends on the used addressing mode. A zero
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// entry in these tables means that the combination of mnemonic and addressing
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// mode is illegal.
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// | 6502 | 65c02 | 65816 | 6510 illegals |
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enum { IDX_ORA,IDX_AND,IDX_EOR,IDX_ADC,IDX_STA,IDX_LDA,IDX_CMP,IDX_SBC,IDXcORA,IDXcAND,IDXcEOR,IDXcADC,IDXcSTA,IDXcLDA,IDXcCMP,IDXcSBC,IDX816ORA,IDX816AND,IDX816EOR,IDX816ADC,IDX816STA,IDX816LDA,IDX816CMP,IDX816SBC,IDX816PEI,IDX_SLO,IDX_RLA,IDX_SRE,IDX_RRA,IDX_SAX,IDX_LAX,IDX_DCP,IDX_ISC};
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SCL accu_abs[] = { 0x0d05, 0x2d25, 0x4d45, 0x6d65, 0x8d85, 0xada5, 0xcdc5, 0xede5, 0x0d05, 0x2d25, 0x4d45, 0x6d65, 0x8d85, 0xada5, 0xcdc5, 0xede5, 0x0f0d05, 0x2f2d25, 0x4f4d45, 0x6f6d65, 0x8f8d85, 0xafada5, 0xcfcdc5, 0xefede5, 0, 0x0f07, 0x2f27, 0x4f47, 0x6f67, 0x8f87, 0xafa7, 0xcfc7, 0xefe7}; // $ff $ffff $ffffff
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SCL accu_xabs[] = { 0x1d15, 0x3d35, 0x5d55, 0x7d75, 0x9d95, 0xbdb5, 0xddd5, 0xfdf5, 0x1d15, 0x3d35, 0x5d55, 0x7d75, 0x9d95, 0xbdb5, 0xddd5, 0xfdf5, 0x1f1d15, 0x3f3d35, 0x5f5d55, 0x7f7d75, 0x9f9d95, 0xbfbdb5, 0xdfddd5, 0xfffdf5, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7}; // $ff,x $ffff,x $ffffff,x
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SCS accu_yabs[] = { 0x1900, 0x3900, 0x5900, 0x7900, 0x9900, 0xb900, 0xd900, 0xf900, 0x1900, 0x3900, 0x5900, 0x7900, 0x9900, 0xb900, 0xd900, 0xf900, 0x1900, 0x3900, 0x5900, 0x7900, 0x9900, 0xb900, 0xd900, 0xf900, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00}; // $ff,y $ffff,y
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SCB accu_xind8[] = { 0x01, 0x21, 0x41, 0x61, 0x81, 0xa1, 0xc1, 0xe1, 0x01, 0x21, 0x41, 0x61, 0x81, 0xa1, 0xc1, 0xe1, 0x01, 0x21, 0x41, 0x61, 0x81, 0xa1, 0xc1, 0xe1, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3}; // ($ff,x)
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SCB accu_indy8[] = { 0x11, 0x31, 0x51, 0x71, 0x91, 0xb1, 0xd1, 0xf1, 0x11, 0x31, 0x51, 0x71, 0x91, 0xb1, 0xd1, 0xf1, 0x11, 0x31, 0x51, 0x71, 0x91, 0xb1, 0xd1, 0xf1, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3}; // ($ff),y
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SCB accu_imm[] = { 0x09, 0x29, 0x49, 0x69, 0, 0xa9, 0xc9, 0xe9, 0x09, 0x29, 0x49, 0x69, 0, 0xa9, 0xc9, 0xe9, 0x09, 0x29, 0x49, 0x69, 0, 0xa9, 0xc9, 0xe9, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // #$ff #$ffff
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SCB accu_ind8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0x12, 0x32, 0x52, 0x72, 0x92, 0xb2, 0xd2, 0xf2, 0x12, 0x32, 0x52, 0x72, 0x92, 0xb2, 0xd2, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff)
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SCB accu_sabs8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff,s
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SCB accu_sindy8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x13, 0x33, 0x53, 0x73, 0x93, 0xb3, 0xd3, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y
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SCB accu_lind8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x07, 0x27, 0x47, 0x67, 0x87, 0xa7, 0xc7, 0xe7, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff]
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SCB accu_lindy8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x17, 0x37, 0x57, 0x77, 0x97, 0xb7, 0xd7, 0xf7, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],y
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// | 6502 | 65c02 | 65816 | 6510 illegals |
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enum { IDX_ORA,IDX_AND,IDX_EOR,IDX_ADC,IDX_STA,IDX_LDA,IDX_CMP,IDX_SBC,IDXcORA,IDXcAND,IDXcEOR,IDXcADC,IDXcSTA,IDXcLDA,IDXcCMP,IDXcSBC,IDX816ORA,IDX816AND,IDX816EOR,IDX816ADC,IDX816STA,IDX816LDA,IDX816CMP,IDX816SBC,IDX816PEI,IDX_SLO,IDX_RLA,IDX_SRE,IDX_RRA,IDX_SAX,IDX_LAX,IDX_DCP,IDX_ISC,IDX_SHA};
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SCL accu_abs[] = { 0x0d05, 0x2d25, 0x4d45, 0x6d65, 0x8d85, 0xada5, 0xcdc5, 0xede5, 0x0d05, 0x2d25, 0x4d45, 0x6d65, 0x8d85, 0xada5, 0xcdc5, 0xede5, 0x0f0d05, 0x2f2d25, 0x4f4d45, 0x6f6d65, 0x8f8d85, 0xafada5, 0xcfcdc5, 0xefede5, 0, 0x0f07, 0x2f27, 0x4f47, 0x6f67, 0x8f87, 0xafa7, 0xcfc7, 0xefe7, 0}; // $ff $ffff $ffffff
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SCL accu_xabs[] = { 0x1d15, 0x3d35, 0x5d55, 0x7d75, 0x9d95, 0xbdb5, 0xddd5, 0xfdf5, 0x1d15, 0x3d35, 0x5d55, 0x7d75, 0x9d95, 0xbdb5, 0xddd5, 0xfdf5, 0x1f1d15, 0x3f3d35, 0x5f5d55, 0x7f7d75, 0x9f9d95, 0xbfbdb5, 0xdfddd5, 0xfffdf5, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x
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SCS accu_yabs[] = { 0x1900, 0x3900, 0x5900, 0x7900, 0x9900, 0xb900, 0xd900, 0xf900, 0x1900, 0x3900, 0x5900, 0x7900, 0x9900, 0xb900, 0xd900, 0xf900, 0x1900, 0x3900, 0x5900, 0x7900, 0x9900, 0xb900, 0xd900, 0xf900, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y
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SCB accu_xind8[] = { 0x01, 0x21, 0x41, 0x61, 0x81, 0xa1, 0xc1, 0xe1, 0x01, 0x21, 0x41, 0x61, 0x81, 0xa1, 0xc1, 0xe1, 0x01, 0x21, 0x41, 0x61, 0x81, 0xa1, 0xc1, 0xe1, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0}; // ($ff,x)
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SCB accu_indy8[] = { 0x11, 0x31, 0x51, 0x71, 0x91, 0xb1, 0xd1, 0xf1, 0x11, 0x31, 0x51, 0x71, 0x91, 0xb1, 0xd1, 0xf1, 0x11, 0x31, 0x51, 0x71, 0x91, 0xb1, 0xd1, 0xf1, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y
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SCB accu_imm[] = { 0x09, 0x29, 0x49, 0x69, 0, 0xa9, 0xc9, 0xe9, 0x09, 0x29, 0x49, 0x69, 0, 0xa9, 0xc9, 0xe9, 0x09, 0x29, 0x49, 0x69, 0, 0xa9, 0xc9, 0xe9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // #$ff #$ffff
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SCB accu_ind8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0x12, 0x32, 0x52, 0x72, 0x92, 0xb2, 0xd2, 0xf2, 0x12, 0x32, 0x52, 0x72, 0x92, 0xb2, 0xd2, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff)
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SCB accu_sabs8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff,s
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SCB accu_sindy8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x13, 0x33, 0x53, 0x73, 0x93, 0xb3, 0xd3, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y
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||||
SCB accu_lind8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x07, 0x27, 0x47, 0x67, 0x87, 0xa7, 0xc7, 0xe7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff]
|
||||
SCB accu_lindy8[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x17, 0x37, 0x57, 0x77, 0x97, 0xb7, 0xd7, 0xf7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],y
|
||||
|
||||
// Code tables for group GROUP_MISC:
|
||||
// These tables are needed for finding out the correct code in cases when
|
||||
|
|
@ -109,13 +109,13 @@ SCB accu_lindy8[] = { 0, 0, 0, 0, 0, 0, 0,
|
|||
// mnemotable), the assembler finds out the column to use here. The row
|
||||
// depends on the used addressing mode. A zero entry in these tables means
|
||||
// that the combination of mnemonic and addressing mode is illegal.
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||||
// | 6502 | 65c02 | 65816 | 6510 illegals | C64DTV2 |
|
||||
enum { IDX_BIT,IDX_ASL,IDX_ROL,IDX_LSR,IDX_ROR,IDX_STY,IDX_STX,IDX_LDY,IDX_LDX,IDX_CPY,IDX_CPX,IDX_DEC,IDX_INC,IDXcTSB,IDXcTRB,IDXcBIT,IDXcDEC,IDXcINC,IDXcSTZ,IDX816COP,IDX816REP,IDX816SEP,IDX816PEA,IDX_ANC,IDX_ASR,IDX_ARR,IDX_SBX,IDX_DOP,IDX_TOP,IDX_JAM,IDX_LXA,IDX_SAC,IDX_SIR};
|
||||
SCS misc_abs[] = { 0x2c24, 0x0e06, 0x2e26, 0x4e46, 0x6e66, 0x8c84, 0x8e86, 0xaca4, 0xaea6, 0xccc4, 0xece4, 0xcec6, 0xeee6, 0x0c04, 0x1c14, 0x2c24, 0xcec6, 0xeee6, 0x9c64, 0x02, 0, 0, 0xf400, 0, 0, 0, 0, 0x04, 0x0c00, 0, 0, 0, 0}; // $ff $ffff
|
||||
SCS misc_xabs[] = { 0, 0x1e16, 0x3e36, 0x5e56, 0x7e76, 0x94, 0, 0xbcb4, 0, 0, 0, 0xded6, 0xfef6, 0, 0, 0x3c34, 0xded6, 0xfef6, 0x9e74, 0, 0, 0, 0, 0, 0, 0, 0, 0x14, 0x1c00, 0, 0, 0, 0}; // $ff,x $ffff,x
|
||||
SCS misc_yabs[] = { 0, 0, 0, 0, 0, 0, 0x96, 0, 0xbeb6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff,y $ffff,y
|
||||
SCB misc_imm[] = { 0, 0, 0, 0, 0, 0, 0, 0xa0, 0xa2, 0xc0, 0xe0, 0, 0, 0, 0, 0x89, 0, 0, 0, 0, 0xc2, 0xe2, 0, 0x0b, 0x4b, 0x6b, 0xcb, 0x80, 0, 0, 0xab, 0x32, 0x42}; // #$ff
|
||||
SCB misc_impl[] = { 0, 0x0a, 0x2a, 0x4a, 0x6a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x3a, 0x1a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x0c, 0x02, 0, 0, 0}; // implied/accu
|
||||
// | 6502 | 65c02 | 65816 | 6510 illegals | C64DTV2 |
|
||||
enum { IDX_BIT,IDX_ASL,IDX_ROL,IDX_LSR,IDX_ROR,IDX_STY,IDX_STX,IDX_LDY,IDX_LDX,IDX_CPY,IDX_CPX,IDX_DEC,IDX_INC,IDXcTSB,IDXcTRB,IDXcBIT,IDXcDEC,IDXcINC,IDXcSTZ,IDX816COP,IDX816REP,IDX816SEP,IDX816PEA,IDX_ANC,IDX_ASR,IDX_ARR,IDX_SBX,IDX_DOP,IDX_TOP,IDX_JAM,IDX_LXA,IDX_ANE,IDX_LAS,IDX_TAS,IDX_SHX,IDX_SHY,IDX_SAC,IDX_SIR};
|
||||
SCS misc_abs[] = { 0x2c24, 0x0e06, 0x2e26, 0x4e46, 0x6e66, 0x8c84, 0x8e86, 0xaca4, 0xaea6, 0xccc4, 0xece4, 0xcec6, 0xeee6, 0x0c04, 0x1c14, 0x2c24, 0xcec6, 0xeee6, 0x9c64, 0x02, 0, 0, 0xf400, 0, 0, 0, 0, 0x04, 0x0c00, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff $ffff
|
||||
SCS misc_xabs[] = { 0, 0x1e16, 0x3e36, 0x5e56, 0x7e76, 0x94, 0, 0xbcb4, 0, 0, 0, 0xded6, 0xfef6, 0, 0, 0x3c34, 0xded6, 0xfef6, 0x9e74, 0, 0, 0, 0, 0, 0, 0, 0, 0x14, 0x1c00, 0, 0, 0, 0, 0, 0, 0x9c00, 0, 0}; // $ff,x $ffff,x
|
||||
SCS misc_yabs[] = { 0, 0, 0, 0, 0, 0, 0x96, 0, 0xbeb6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xbb00, 0x9b00, 0x9e00, 0, 0, 0}; // $ff,y $ffff,y
|
||||
SCB misc_imm[] = { 0, 0, 0, 0, 0, 0, 0, 0xa0, 0xa2, 0xc0, 0xe0, 0, 0, 0, 0, 0x89, 0, 0, 0, 0, 0xc2, 0xe2, 0, 0x0b, 0x4b, 0x6b, 0xcb, 0x80, 0, 0, 0xab, 0x8b, 0, 0, 0, 0, 0x32, 0x42}; // #$ff
|
||||
SCB misc_impl[] = { 0, 0x0a, 0x2a, 0x4a, 0x6a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x3a, 0x1a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x0c, 0x02, 0, 0, 0, 0, 0, 0, 0, 0}; // implied/accu
|
||||
|
||||
// Code tables for group GROUP_ALLJUMPS:
|
||||
// These tables are needed for finding out the correct code when the mnemonic
|
||||
|
|
@ -227,18 +227,24 @@ static struct ronode mnemos_6510[] = {
|
|||
PREDEFNODE("rla", MERGE(GROUP_ACCU, IDX_RLA)), // ROL + AND
|
||||
PREDEFNODE("sre", MERGE(GROUP_ACCU, IDX_SRE)), // LSR + EOR (aka LSE)
|
||||
PREDEFNODE("rra", MERGE(GROUP_ACCU, IDX_RRA)), // ROR + ADC
|
||||
PREDEFNODE("sax", MERGE(GROUP_ACCU, IDX_SAX)), // STX + STA (aka AAX aka AXS)
|
||||
PREDEFNODE("sax", MERGE(GROUP_ACCU, IDX_SAX)), // STX + STA (aka AXS aka AAX)
|
||||
PREDEFNODE("lax", MERGE(GROUP_ACCU, IDX_LAX)), // LDX + LDA
|
||||
PREDEFNODE("dcp", MERGE(GROUP_ACCU, IDX_DCP)), // DEC + CMP (aka DCM)
|
||||
PREDEFNODE("isc", MERGE(GROUP_ACCU, IDX_ISC)), // INC + SBC (aka ISB aka INS)
|
||||
PREDEFNODE("las", MERGE(GROUP_MISC, IDX_LAS)), // A,X,S = {addr} & S (aka LAR aka LAE)
|
||||
PREDEFNODE("tas", MERGE(GROUP_MISC, IDX_TAS)), // S = A & X {addr} = A&X& {H+1} (aka SHS aka XAS)
|
||||
PREDEFNODE("sha", MERGE(GROUP_ACCU, IDX_SHA)), // {addr} = A & X & {H+1} (aka AXA aka AHX)
|
||||
PREDEFNODE("shx", MERGE(GROUP_MISC, IDX_SHX)), // {addr} = X & {H+1} (aka XAS aka SXA)
|
||||
PREDEFNODE("shy", MERGE(GROUP_MISC, IDX_SHY)), // {addr} = Y & {H+1} (aka SAY aka SYA)
|
||||
PREDEFNODE("anc", MERGE(GROUP_MISC, IDX_ANC)), // ROL + AND, ASL + ORA (aka AAC)
|
||||
PREDEFNODE(s_asr, MERGE(GROUP_MISC, IDX_ASR)), // LSR + EOR (aka ALR)
|
||||
PREDEFNODE("arr", MERGE(GROUP_MISC, IDX_ARR)), // ROR + ADC
|
||||
PREDEFNODE("sbx", MERGE(GROUP_MISC, IDX_SBX)), // DEX + CMP (aka AXS aka SAX)
|
||||
PREDEFNODE("dop", MERGE(GROUP_MISC, IDX_DOP)), // skip next byte
|
||||
PREDEFNODE("top", MERGE(GROUP_MISC, IDX_TOP)), // skip next two bytes
|
||||
PREDEFNODE("top", MERGE(GROUP_MISC, IDX_TOP)), // skip next word
|
||||
PREDEFNODE("jam", MERGE(GROUP_MISC, IDX_JAM)), // jam/crash/kill/halt-and-catch-fire
|
||||
PREDEFLAST("lxa", MERGE(GROUP_MISC, IDX_LXA)), // ORA #?? + AND #arg + TAX (aka OAL aka ATX)
|
||||
PREDEFNODE("ane", MERGE(GROUP_MISC, IDX_ANE)), // A = (A | ??) & X & arg (aka XAA)
|
||||
PREDEFLAST("lxa", MERGE(GROUP_MISC, IDX_LXA)), // A,X = (A | ??) & arg (aka OAL aka ATX)
|
||||
// ^^^^ this marks the last element
|
||||
};
|
||||
|
||||
|
|
@ -768,12 +774,15 @@ static void group_misc(int index, int imm_flag)
|
|||
// CAUTION - do not incorporate the line above into the line
|
||||
// below - "force_bit" might be undefined (depends on compiler).
|
||||
make_command(force_bit, &result, imm_opcodes);
|
||||
// check whether to warn about 6510's unstable LXA
|
||||
if ((imm_opcodes == 0xab)
|
||||
// check whether to warn about 6510's unstable ANE/LXA
|
||||
if ((CPU_state.type->flags & CPUFLAG_8B_AND_AB_NEED_0_ARG)
|
||||
&& ((result.val.intval & 0xff) != 0x00)
|
||||
&& (result.flags & MVALUE_DEFINED)
|
||||
&& (CPU_state.type->flags & CPUFLAG_AB_NEEDS_0_ARG))
|
||||
Throw_warning("Assembling unstable LXA #NONZERO instruction");
|
||||
&& (result.flags & MVALUE_DEFINED)) {
|
||||
if (imm_opcodes == 0x8b)
|
||||
Throw_warning("Assembling unstable ANE #NONZERO instruction");
|
||||
else if (imm_opcodes == 0xab)
|
||||
Throw_warning("Assembling unstable LXA #NONZERO instruction");
|
||||
}
|
||||
break;
|
||||
case HAM_ABS: // $ff or $ffff
|
||||
make_command(force_bit, &result, misc_abs[index]);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user