marcobaye
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b03b217979
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disabled all indexed addressing for m65's "quad" mode, except for LDQ.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@287 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-29 23:30:33 +00:00 |
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marcobaye
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6dd15f7116
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added BITQ and ASRQ to m65 cpu.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@283 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-27 23:37:36 +00:00 |
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marcobaye
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70b9ee222d
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tweaked docs and removed some comments, no change in functionality
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@273 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-06-30 09:24:30 +00:00 |
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marcobaye
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a7dd713d93
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cleaned up list of cpu types and added opcode table(s) for m65 cpu
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@272 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-06-29 15:10:42 +00:00 |
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