marcobaye
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b03b217979
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disabled all indexed addressing for m65's "quad" mode, except for LDQ.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@287 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-29 23:30:33 +00:00 |
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marcobaye
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3db33bafb5
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nmos6502 mode now also accepts ALR mnemonic (alias for ASR)
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@286 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-28 23:08:07 +00:00 |
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marcobaye
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26168e6752
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small change in tests, improved 65816 register length checking
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@285 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-28 13:13:26 +00:00 |
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marcobaye
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2acece9c60
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added test script
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@284 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-28 12:57:26 +00:00 |
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marcobaye
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6dd15f7116
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added BITQ and ASRQ to m65 cpu.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@283 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-27 23:37:36 +00:00 |
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marcobaye
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f87ddbb5e6
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added last cpu test source and expected output
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@282 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-27 22:58:10 +00:00 |
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marcobaye
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32d59eafa3
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still more test sources and expected outputs
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@281 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-27 22:09:27 +00:00 |
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marcobaye
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a3d36ca156
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more test sources and expected outputs
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@280 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-27 21:25:39 +00:00 |
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marcobaye
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78390cb632
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added more test sources
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@279 4df02467-bbd4-4a76-a152-e7ce94205b78
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2020-07-27 19:47:07 +00:00 |
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