acme/docs/cputypes.txt
marcobaye 294fe25c36 ACME Release 0.96: Added experimental support for instruction sets of Rockwell 65C02, WDC 65C02(S), CSG 65CE02 and CSG 4502.
Stack indexing can now be given either as ",s" or as ",sp" (only relevant for 65816 and 65CE02).


git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@78 4df02467-bbd4-4a76-a152-e7ce94205b78
2016-12-28 20:32:00 +00:00

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ACME
...the ACME Crossassembler for Multiple Environments
--- cpu types ---
ACME supports the following cpu types:
*** 6502
This is the instruction set of the original NMOS 6502 designed by MOS
(later CSG).
There are 151 documented opcodes.
*** 6510
This is the 6502 variant used in the C64 computer. It uses the same
instruction set as the 6502, but in addition to that, ACME supports
most of the undocumented opcodes as well.
See docs/Illegals.txt for more info.
*** 65c02
This is the CMOS re-design of the 6502. It seems to have also been
available from Rockwell, GTE/CMD and others. Features:
- new instructions:
BRA (branch always)
PHX, PHY, PLX, PLY (push/pull X/Y register)
STZ (store zero, 4 addr modes)
TRB (test and reset bits, 2 addr modes)
TSB (test and set bits, 2 addr modes)
- new addressing modes for existing instructions:
BIT #$12
BIT $12, x
BIT $1234, x
LDA/STA/ADC/SBC ($12) (zp indirect without index)
AND/ORA/EOR/CMP ($12) (zp indirect without index)
INC (increment accumulator)
DEC (decrement accumulator)
JMP ($1234,x) (jump indexed indirect)
- bugfix for flags in decimal mode
- bugfix for JMP($xxff) instruction
- undocumented opcodes are NOPs (although of different lengths)
There are 178 documented opcodes.
*** r65c02
This is a superset of 65c02, probably originally from Rockwell.
- It adds bit manipulation instructions:
BBR0..BBR7 (branch on bit reset)
BBS0..BBS7 (branch on bit set)
RMB0..RMB7 (reset memory bit)
SMB0..SMB7 (set memory bit)
Chips with this instruction set seem to have been available from
Rockwell, GTE/CMD and others.
There are 210 documented opcodes.
*** w65c02
This is a superset of r65c02, originating at WDC.
- It adds the STP and WAI instructions.
There are 212 documented opcodes.
*** 65816
This is a superset of 65c02, originally designed by WDC (it seems to
have been available from GTE/CMD as well). Features:
- register sizes can be changed to 16-bit
- 24-bit address space
- several new addressing modes
- block transfers
There are 256 documented opcodes, but one of them ("WDM") is reserved
for future expansion.
*** 65ce02
This is a superset of r65c02, originating at CSG. Features:
- Z register
- 16-bit stack pointer
- 16-bit branches
- a few 16-bit instructions
- new addressing modes
There is a known bug: SBC does not work corrently in decimal mode.
There are 256 documented opcodes, but one of them ("AUG") is reserved
for future expansion.
*** 4502
This is basically the same as 65ce02, but
- MAP replaces AUG
- EOM is synonymous to NOP
This cpu core can be found in the CSG4510 chip in the C65.
There are 256 documented opcodes.
*** c64dtv2
This is the cpu in version 2 of the C64DTV. It uses a superset of the
6502 instruction set. Features:
- new instructions:
BRA $1234 (branch always)
SAC #$12 (set accumulator mapping)
SIR #$12 (set index register mapping)
- support for some of the undocumented opcodes.