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143 lines
3.9 KiB
Plaintext
143 lines
3.9 KiB
Plaintext
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ACME
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...the ACME Crossassembler for Multiple Environments
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--- cpu types ---
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ACME supports the following cpu types:
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*** 6502
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This is the instruction set of the original NMOS 6502 designed by MOS
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(later CSG).
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There are 151 documented opcodes.
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ACME does not use "A" to indicate "accumulator addressing"; just write
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the mnemonic without any argument: "LSR" will work, "LSR A" won't.
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*** 6510
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This is the 6502 variant used in the C64 computer. It uses the same
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instruction set as the 6502, but in addition to that, ACME supports
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most of the undocumented opcodes as well.
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See "docs/Illegals.txt" for more info.
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*** 65c02
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This is the CMOS re-design of the 6502. It seems to have also been
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available from Rockwell, GTE/CMD and others. Features:
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- new instructions:
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BRA near_target branch always
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PHX/PHY/PLX/PLY push/pull X/Y register
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STZ $12 store zero in zp
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STZ $12, x store zero in zp, x-indexed
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STZ $1234 store zero absolute
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STZ $1234, x store zero absolute, x-indexed
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TRB $12 test and reset bits in zp
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TRB $1234 test and reset bits absolute
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TSB $12 test and set bits in zp
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TSB $1234 test and set bits absolute
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- new addressing modes for existing instructions:
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LDA/STA/ADC/SBC ($12) zp indirect
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AND/ORA/EOR/CMP ($12) zp indirect
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BIT #$12 immediate
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BIT $12, x zp, x-indexed
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BIT $1234, x absolute, x-indexed
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INC increment accumulator
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DEC decrement accumulator
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JMP ($1234, x) x-indexed indirect
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- bugfix for flags in decimal mode
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- bugfix for JMP($xxff) instruction
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- undocumented opcodes are NOPs (although of different lengths)
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There are 178 documented opcodes.
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*** r65c02
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This is a superset of 65c02, probably originally by Rockwell. It adds
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bit manipulation instructions:
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BBR0 $12, near_target branch on bit reset in zp
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BBS0 $12, near_target branch on bit set in zp
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RMB0 $12 reset memory bit in zp
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SMB0 $12 set memory bit in zp
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The digit in the mnemonic is the bit number, therefore it must be in
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the 0..7 range.
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Chips with this instruction set seem to have been available from
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Rockwell, GTE/CMD and others.
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There are 210 documented opcodes.
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*** w65c02
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This is a superset of r65c02, originating at WDC. It adds two new
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instructions:
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STP stop (wait for reset)
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WAI wait for interrupt
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There are 212 documented opcodes.
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*** 65816
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This is a superset of 65c02, originally designed by WDC (it seems to
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have been available from GTE/CMD as well). Features:
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- register sizes can be changed to 16-bit
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- 24-bit address space
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- several new instructions (including block transfers)
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- several new addressing modes for existing instructions
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There are 256 documented opcodes, but one of them ("WDM") is reserved
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for future expansion.
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See "docs/65816.txt" for more info.
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*** 65ce02
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This is a superset of r65c02, originating at CSG. Features:
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- Z register
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- 16-bit stack pointer
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- 16-bit branches
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- new instructions (including a few 16-bit operations)
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- new addressing modes for existing instructions
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There is a known bug: SBC does not work correctly in decimal mode.
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There are 256 documented opcodes, but one of them ("AUG") is reserved
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for future expansion.
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ACME uses different mnemonics for old and new (long) branch
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instructions:
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BEQ near_target old, 8-bit offset
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LBEQ far_target new, 16-bit offset
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The original datasheet called BRA ("branch always") BRU ("branch
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unconditional") instead. ACME accepts both mnemonics.
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*** 4502
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This is basically the same as 65ce02, but
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- MAP replaces AUG
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- EOM is synonymous to NOP
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This cpu core can be found in the CSG4510 chip in the C65.
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There are 256 documented opcodes.
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*** c64dtv2
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This is the cpu in version 2 of the C64DTV. It uses a superset of the
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6502 instruction set. Features:
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- new instructions:
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BRA near_target branch always
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SAC #$12 set accumulator mapping
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SIR #$12 set index register mapping
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- support for some of the undocumented opcodes.
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