mirror of https://github.com/uffejakobsen/acme.git
225 lines
6.5 KiB
Plaintext
225 lines
6.5 KiB
Plaintext
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ACME
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...the ACME Crossassembler for Multiple Environments
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--- cpu types ---
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ACME supports the following cpu types (shown here as a sort of family
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tree):
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6502 standard
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|\_nmos6502 (=6510) + undocumented opcodes
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|\_c64dtv2 + BRA/SAC/SIR and some (not all!) undocumented
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\_65c02 + BRA/PHX/PHY/PLX/PLY/STZ/TRB/TSB/...
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|\_65816 16 bit regs, 24 bit address space, ...
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\_r65c02 + bit manipulation instructions
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|\_w65c02 + STP/WAI
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\_65ce02 + Z reg, long branches, ...
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\_4502 + MAP/EOM
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\_m65 + 32-bit pointers, 32-bit 'Q' register
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!cpu 6502
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This is the official instruction set of the original NMOS 6502 CPU
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designed by MOS (later CSG).
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There are 151 documented opcodes.
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ACME does not use "A" to indicate "accumulator addressing"; just write
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the mnemonic without any argument: "LSR" will work, "LSR A" won't.
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!cpu nmos6502
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This instruction set includes the undocumented ("illegal") opcodes of
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the NMOS 6502.
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See "docs/Illegals.txt" for more info.
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!cpu 6510
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This is an alias for "nmos6502", because the 6510 cpu (as used in the
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C64 computer) is a variant of this type.
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!cpu c64dtv2
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This is the cpu in version 2 of the C64DTV. It uses a superset of the
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6502 instruction set. Features:
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- new instructions:
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BRA near_target branch always
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SAC #$12 set accumulator mapping
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SIR #$12 set index register mapping
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- support for some (but not all!) of the undocumented opcodes.
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!cpu 65c02
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This is the CMOS re-design of the 6502. It seems to have also been
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available from Rockwell, GTE/CMD and others. Features:
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- new instructions:
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BRA near_target branch always
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PHX/PHY/PLX/PLY push/pull X/Y register
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STZ $12 store zero in zp
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STZ $12, x store zero in zp, x-indexed
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STZ $1234 store zero absolute
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STZ $1234, x store zero absolute, x-indexed
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TRB $12 test and reset bits in zp
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TRB $1234 test and reset bits absolute
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TSB $12 test and set bits in zp
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TSB $1234 test and set bits absolute
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- new addressing modes for existing instructions:
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LDA/STA/ADC/SBC ($12) zp indirect
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AND/ORA/EOR/CMP ($12) zp indirect
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BIT #$12 immediate
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BIT $12, x zp, x-indexed
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BIT $1234, x absolute, x-indexed
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INC increment accumulator
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DEC decrement accumulator
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JMP ($1234, x) x-indexed indirect
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- bugfix for flags in decimal mode
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- bugfix for JMP($xxff) instruction
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- undocumented opcodes are NOPs (although of different lengths)
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There are 178 documented opcodes.
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!cpu 65816
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This is a superset of 65c02, originally designed by WDC (it seems to
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have been available from GTE/CMD as well). Features:
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- register sizes can be changed to 16-bit
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- 24-bit address space
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- several new instructions (including block transfers)
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- several new addressing modes for existing instructions
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There are 256 documented opcodes, but one of them ("WDM") is reserved
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for future expansion.
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See "docs/65816.txt" for more info.
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!cpu r65c02
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This is a superset of 65c02, probably originally by Rockwell. It adds
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bit manipulation instructions:
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BBR4 $12, near_target branch on bit reset in zp
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BBS5 $12, near_target branch on bit set in zp
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RMB6 $12 reset memory bit in zp
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SMB7 $12 set memory bit in zp
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The digit in the mnemonic is the bit number, therefore it must be in
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the 0..7 range.
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Chips with this instruction set seem to have been available from
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Rockwell, GTE/CMD and others.
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There are 210 documented opcodes.
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!cpu w65c02
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This is a superset of r65c02, originating at WDC. It adds two new
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instructions:
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STP stop (wait for reset)
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WAI wait for interrupt
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There are 212 documented opcodes.
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!cpu 65ce02
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This is a superset of r65c02, originating at CSG. Features:
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- Z register
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- 16-bit stack pointer
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- 16-bit branches
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- new instructions (including a few 16-bit operations)
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- new addressing modes for existing instructions
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There is a known bug: SBC does not work correctly in decimal mode.
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There are 256 documented opcodes, but one of them ("AUG") is reserved
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for future expansion.
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ACME uses different mnemonics for old and new (long) branch
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instructions:
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BEQ near_target old, 8-bit offset
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LBEQ far_target new, 16-bit offset
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The original datasheet called BRA ("branch always") BRU ("branch
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unconditional") instead. ACME accepts both mnemonics.
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!cpu 4502
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This is basically the same as 65ce02, but
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- MAP replaces AUG
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- EOM is synonymous to NOP
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This cpu core can be found in the CSG4510 chip in the C65.
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There are 256 documented opcodes.
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!cpu m65
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This is a superset of 4502 specified by the MEGA65 project. It uses
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NEG:NEG and NOP as prefix bytes to extend the instruction set.
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Features:
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- "quad mode" (32-bit data operations on virtual register 'Q')
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- "long mode" (32-bit pointer addressing for existing mnemonics)
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- "quad" and "long" modes can be combined
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quad mode introduces several new mnemonics:
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LDQ/STQ/CPQ like LDA/STA/CMP
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ADCQ/SBCQ like ADC/SBC
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ANDQ/EORQ/ORQ like AND/EOR/ORA
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ASLQ/LSRQ/ROLQ/RORQ like ASL/LSR/ROL/ROR
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INQ/DEQ like INC/DEC
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BITQ like BIT
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ASRQ like ASR
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The new mnemonics support most of the addressing modes of the
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original mnemonics with these exceptions:
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- there is no immediate addressing
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- indirect-Z-indexed addressing becomes indirect addressing
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- all other indexed addressing modes can only really be used
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with read-modify-write instructions or LDQ, because otherwise
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a part of the 'Q' value would be used as the index.
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CAUTION: The STQ instruction clobbers the N and Z flags!
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There is no "real" Q register, instead A/X/Y/Z are combined to form
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the Q register (A holds lsb, Z holds msb), except for read-modify-
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write instructions, where the 32-bit operation is performed without
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using A/X/Y/Z.
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To load a 32-bit immediate constant into the Q register, use the
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+movq macro from the <m65/std.a> library file.
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long mode brings a single new addressing mode for eight mnemonics:
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LDA [$12], z contents of $12/$13/$14/$15
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STA [$12], z plus z form the address
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CMP [$12], z
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ADC [$12], z
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SBC [$12], z
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AND [$12], z
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EOR [$12], z
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ORA [$12], z
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quad and long modes combined result in another addressing mode for
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eight of the new mnemonics:
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LDQ [$12] contents of $12/$13/$14/$15
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STQ [$12] form the address
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CPQ [$12]
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ADCQ [$12]
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SBCQ [$12]
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ANDQ [$12]
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EORQ [$12]
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ORQ [$12]
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The NOP mnemonic is disabled for this instruction set because its
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opcode is re-used internally as a prefix byte.
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CAUTION: The !align pseudo opcode still inserts NOPs.
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