2004-10-08 18:14:19 +00:00
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; ***
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; CC65 Lynx Library
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;
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; Originally by Bastian Schick
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; http://www.geocities.com/SiliconValley/Byte/4242/lynx/
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;
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; Ported to cc65 (http://www.cc65.org) by
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; Shawn Jefferson, June 2004
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;
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; ***
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;
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2014-08-23 18:05:36 +00:00
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; Startup code for cc65 (Lynx version). Based on the Atari 8-bit startup
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2004-10-08 18:14:19 +00:00
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; code structure. The C stack is located at the end of the RAM memory
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2014-08-23 18:05:36 +00:00
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; segment, and grows downward. Bastian Schick's executable header is put
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2004-10-08 18:14:19 +00:00
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; on the front of the fully linked binary (see EXEHDR segment.)
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;
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2013-05-09 11:56:54 +00:00
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.export _exit
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.export __STARTUP__ : absolute = 1 ; Mark as startup
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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.import initlib, donelib
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.import zerobss
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.import callmain
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.import _main
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.import __RAM_START__, __RAM_SIZE__, __STACKSIZE__
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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.include "zeropage.inc"
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.include "extzp.inc"
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.include "lynx.inc"
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2004-10-08 18:14:19 +00:00
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; ------------------------------------------------------------------------
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; Mikey and Suzy init data, reg offsets and data
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2013-05-09 11:56:54 +00:00
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.rodata
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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SuzyInitReg: .byte $28,$2a,$04,$06,$92,$83,$90
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SuzyInitData: .byte $7f,$7f,$00,$00,$24,$f3,$01
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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MikeyInitReg: .byte $00,$01,$08,$09,$20,$28,$30,$38,$44,$50,$8a,$8b,$8c,$92,$93
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MikeyInitData: .byte $9e,$18,$68,$1f,$00,$00,$00,$00,$00,$ff,$1a,$1b,$04,$0d,$29
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2004-10-08 18:14:19 +00:00
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; ------------------------------------------------------------------------
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; Actual code
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2013-05-09 11:56:54 +00:00
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.segment "STARTUP"
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Set up the system.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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sei
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cld
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ldx #$FF
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txs
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Init the bank switching.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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lda #$C
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sta MAPCTL ; $FFF9
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Disable all timer interrupts.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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lda #$80
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trb TIM0CTLA
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trb TIM1CTLA
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trb TIM2CTLA
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trb TIM3CTLA
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trb TIM5CTLA
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trb TIM6CTLA
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trb TIM7CTLA
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Disable the TX/RX IRQ; set to 8E1.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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lda #%11101
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sta SERCTL
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Clear all pending interrupts.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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lda INTSET
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sta INTRST
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Set up the stack.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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lda #<(__RAM_START__ + __RAM_SIZE__ + __STACKSIZE__)
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sta sp
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lda #>(__RAM_START__ + __RAM_SIZE__ + __STACKSIZE__)
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sta sp+1
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Init Mickey.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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ldx #.sizeof(MikeyInitReg)-1
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mloop: ldy MikeyInitReg,x
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lda MikeyInitData,x
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sta $fd00,y
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dex
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bpl mloop
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; These are RAM-shadows of read-only regs.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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ldx #$1b
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stx __iodat
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dex ; $1A
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stx __iodir
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ldx #$d
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stx __viddma
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Init Suzy.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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ldx #.sizeof(SuzyInitReg)-1
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sloop: ldy SuzyInitReg,x
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lda SuzyInitData,x
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sta $fc00,y
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dex
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bpl sloop
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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lda #$24
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sta __sprsys
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cli
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Clear the BSS data.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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jsr zerobss
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2009-09-11 13:56:20 +00:00
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2014-08-23 18:05:36 +00:00
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; Call the module constructors.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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jsr initlib
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Push the command-line arguments; and, call main().
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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jsr callmain
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2004-10-08 18:14:19 +00:00
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2014-08-23 18:05:36 +00:00
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; Call the module destructors. This is also the exit() entry.
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2004-10-08 18:14:19 +00:00
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2013-05-09 11:56:54 +00:00
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_exit: jsr donelib ; Run module destructors
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2004-10-08 18:14:19 +00:00
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; Endless loop
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2013-05-09 11:56:54 +00:00
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noret: bra noret
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