2009-09-20 14:22:04 +00:00
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;
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; Serial driver for the Atari Lynx ComLynx port.
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;
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; Karri Kaksonen, 17.09.2009
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;
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2013-05-09 11:56:54 +00:00
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.include "lynx.inc"
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.include "zeropage.inc"
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.include "ser-kernel.inc"
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.include "ser-error.inc"
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2009-09-20 14:22:04 +00:00
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2014-06-04 21:50:18 +00:00
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.macpack module
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2009-09-20 14:22:04 +00:00
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; ------------------------------------------------------------------------
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; Header. Includes jump table
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2014-06-04 21:50:18 +00:00
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module_header _lynx_comlynx_ser
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2009-09-20 14:22:04 +00:00
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2013-05-09 11:56:54 +00:00
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; Driver signature
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.byte $73, $65, $72 ; "ser"
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.byte SER_API_VERSION ; Serial API version number
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2009-09-20 14:22:04 +00:00
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2013-06-01 09:03:14 +00:00
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; Library reference
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.addr $0000
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; Jump table
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2018-11-26 20:28:40 +00:00
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.addr SER_INSTALL
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.addr SER_UNINSTALL
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.addr SER_OPEN
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.addr SER_CLOSE
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.addr SER_GET
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.addr SER_PUT
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.addr SER_STATUS
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.addr SER_IOCTL
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.addr SER_IRQ
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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; Global variables
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;
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2013-05-09 11:56:54 +00:00
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.bss
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2009-09-20 14:22:04 +00:00
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2013-05-09 11:56:54 +00:00
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TxBuffer: .res 256
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RxBuffer: .res 256
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RxPtrIn: .res 1
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RxPtrOut: .res 1
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TxPtrIn: .res 1
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TxPtrOut: .res 1
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contrl: .res 1
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SerialStat: .res 1
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TxDone: .res 1
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2009-09-20 14:22:04 +00:00
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2013-05-09 11:56:54 +00:00
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.code
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_INSTALL: Is called after the driver is loaded into memory.
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2009-09-20 14:22:04 +00:00
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;
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; Must return an SER_ERR_xx code in a/x.
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2018-11-26 20:28:40 +00:00
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SER_INSTALL:
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2013-05-09 11:56:54 +00:00
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; Set up IRQ vector ?
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_UNINSTALL: Is called before the driver is removed from memory.
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2009-09-20 14:22:04 +00:00
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; No return code required (the driver is removed from memory on return).
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;
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2018-11-26 20:28:40 +00:00
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SER_UNINSTALL:
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_CLOSE: Close the port and disable interrupts. Called without parameters.
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2009-09-20 14:22:04 +00:00
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; Must return an SER_ERR_xx code in a/x.
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2018-11-26 20:28:40 +00:00
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SER_CLOSE:
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2024-02-09 00:09:16 +00:00
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; Disable interrupts and stop timer 4 (serial)
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2024-02-11 15:46:23 +00:00
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lda #TXOPEN|RESETERR
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2024-02-09 00:09:16 +00:00
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sta SERCTL
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2024-02-11 23:12:27 +00:00
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stz TIM4CTLA ; Disable count and no reload
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stz SerialStat ; Reset status
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2024-02-09 00:09:16 +00:00
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2013-05-09 11:56:54 +00:00
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; Done, return an error code
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_OK
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.assert SER_ERR_OK = 0, error
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tax
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2013-05-09 11:56:54 +00:00
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rts
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_OPEN: A pointer to a ser_params structure is passed in ptr1.
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2009-09-20 14:22:04 +00:00
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;
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; The Lynx has only two correct serial data formats:
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; 8 bits, parity mark, 1 stop bit
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; 8 bits, parity space, 1 stop bit
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;
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; It also has two wrong formats;
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; 8 bits, even parity, 1 stop bit
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; 8 bits, odd parity, 1 stop bit
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;
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; Unfortunately the parity bit includes itself in the calculation making
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; parity not compatible with the rest of the world.
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;
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; We can only specify a few baud rates.
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; Lynx has two non-standard speeds 31250 and 62500 which are
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; frequently used in games.
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;
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; The receiver will always read the parity and report parity errors.
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;
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; Must return an SER_ERR_xx code in a/x.
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2018-11-26 20:28:40 +00:00
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SER_OPEN:
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2013-05-09 11:56:54 +00:00
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stz RxPtrIn
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stz RxPtrOut
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stz TxPtrIn
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stz TxPtrOut
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ldy #SER_PARAMS::BAUDRATE
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lda (ptr1),y
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2024-02-09 10:42:52 +00:00
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; Source period is 1 us
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ldy #%00011000 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_1
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2013-05-09 11:56:54 +00:00
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ldx #1
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cmp #SER_BAUD_62500
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beq setbaudrate
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2024-02-09 00:09:16 +00:00
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ldx #3
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2013-05-09 11:56:54 +00:00
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cmp #SER_BAUD_31250
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beq setbaudrate
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ldx #12
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cmp #SER_BAUD_9600
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beq setbaudrate
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ldx #25
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cmp #SER_BAUD_4800
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beq setbaudrate
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ldx #51
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cmp #SER_BAUD_2400
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beq setbaudrate
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2024-02-09 10:42:52 +00:00
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ldx #68
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cmp #SER_BAUD_1800
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beq setbaudrate
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2013-05-09 11:56:54 +00:00
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ldx #103
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cmp #SER_BAUD_1200
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beq setbaudrate
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ldx #207
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cmp #SER_BAUD_600
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beq setbaudrate
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2024-02-09 12:54:00 +00:00
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; Source period is 8 us
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2024-02-09 10:42:52 +00:00
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ldy #%00011011 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_8
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2013-05-09 11:56:54 +00:00
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2024-02-09 10:42:52 +00:00
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ldx #51
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cmp #SER_BAUD_300
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2013-05-09 11:56:54 +00:00
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beq setbaudrate
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_BAUD_UNAVAIL
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ldx #0 ; return value is char
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2013-05-09 11:56:54 +00:00
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rts
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2024-02-09 00:09:16 +00:00
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2009-09-20 14:22:04 +00:00
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setbaudrate:
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2024-02-09 10:42:52 +00:00
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sty TIM4CTLA
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2013-05-09 11:56:54 +00:00
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stx TIM4BKUP
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2024-02-09 10:42:52 +00:00
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2024-02-09 00:09:16 +00:00
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ldx #TXOPEN|PAREVEN
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2013-05-09 11:56:54 +00:00
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stx contrl
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ldy #SER_PARAMS::DATABITS ; Databits
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lda (ptr1),y
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cmp #SER_BITS_8
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bne invparameter
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ldy #SER_PARAMS::STOPBITS ; Stopbits
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lda (ptr1),y
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cmp #SER_STOP_1
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bne invparameter
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ldy #SER_PARAMS::PARITY ; Parity
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lda (ptr1),y
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cmp #SER_PAR_NONE
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beq invparameter
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cmp #SER_PAR_MARK
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beq checkhs
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cmp #SER_PAR_SPACE
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bne @L0
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2024-02-09 00:09:16 +00:00
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ldx #TXOPEN
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2013-05-09 11:56:54 +00:00
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stx contrl
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bra checkhs
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2009-09-20 14:22:04 +00:00
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@L0:
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2024-02-09 00:09:16 +00:00
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ldx #PAREN|TXOPEN|PAREVEN
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2013-05-09 11:56:54 +00:00
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stx contrl
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cmp #SER_PAR_EVEN
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beq checkhs
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2024-02-09 00:09:16 +00:00
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ldx #PAREN|TXOPEN
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2013-05-09 11:56:54 +00:00
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stx contrl
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2009-09-20 14:22:04 +00:00
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checkhs:
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2013-05-09 11:56:54 +00:00
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ldx contrl
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stx SERCTL
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ldy #SER_PARAMS::HANDSHAKE ; Handshake
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lda (ptr1),y
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cmp #SER_HS_NONE
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2024-02-11 15:33:22 +00:00
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beq redeye_ok
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cmp #SER_HS_SW ; Software handshake will check for connected redeye
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2013-05-09 11:56:54 +00:00
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bne invparameter
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2024-02-11 15:33:22 +00:00
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lda IODAT
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and #NOEXP ; Check if redeye bit flag is unset
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beq redeye_ok
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lda #SER_ERR_NO_DEVICE ; ComLynx cable is not inserted
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ldx #0
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rts
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redeye_ok:
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2013-05-09 11:56:54 +00:00
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lda SERDAT
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lda contrl
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2024-02-09 00:09:16 +00:00
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ora #RXINTEN|RESETERR ; Turn on interrupts for receive
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2013-05-09 11:56:54 +00:00
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sta SERCTL
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_OK
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.assert SER_ERR_OK = 0, error
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tax
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2013-05-09 11:56:54 +00:00
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rts
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2024-02-11 15:33:22 +00:00
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2009-09-20 14:22:04 +00:00
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invparameter:
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_INIT_FAILED
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ldx #0 ; return value is char
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2013-05-09 11:56:54 +00:00
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rts
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_GET: Will fetch a character from the receive buffer and store it into the
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2009-09-20 14:22:04 +00:00
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; variable pointed to by ptr1. If no data is available, SER_ERR_NO_DATA is
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; returned.
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2018-11-26 20:28:40 +00:00
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SER_GET:
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2013-05-09 11:56:54 +00:00
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lda RxPtrIn
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cmp RxPtrOut
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bne GetByte
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_NO_DATA
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ldx #0 ; return value is char
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2013-05-09 11:56:54 +00:00
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rts
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2009-09-20 14:22:04 +00:00
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GetByte:
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2013-05-09 11:56:54 +00:00
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ldy RxPtrOut
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2018-11-26 20:28:40 +00:00
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lda RxBuffer,y
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2013-05-09 11:56:54 +00:00
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inc RxPtrOut
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2024-02-11 23:12:27 +00:00
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sta (ptr1)
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2013-05-09 11:56:54 +00:00
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ldx #$00
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txa ; Return code = 0
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rts
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_PUT: Output character in A.
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2009-09-20 14:22:04 +00:00
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; Must return an SER_ERR_xx code in a/x.
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2018-11-26 20:28:40 +00:00
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SER_PUT:
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2013-05-09 11:56:54 +00:00
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tax
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lda TxPtrIn
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ina
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cmp TxPtrOut
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bne PutByte
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2024-02-09 00:09:16 +00:00
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_OVERFLOW
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ldx #0 ; return value is char
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2013-05-09 11:56:54 +00:00
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rts
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2024-02-09 00:09:16 +00:00
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2009-09-20 14:22:04 +00:00
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PutByte:
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2013-05-09 11:56:54 +00:00
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ldy TxPtrIn
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txa
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sta TxBuffer,y
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inc TxPtrIn
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2009-09-20 14:22:04 +00:00
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2024-02-09 00:09:16 +00:00
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bit TxDone ; Check bit 7 of TxDone (TXINTEN)
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bmi @L1 ; Was TXINTEN already set?
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2009-09-20 14:22:04 +00:00
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php
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sei
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2024-02-09 00:09:16 +00:00
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lda contrl ; contrl does not include RXINTEN setting
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ora #TXINTEN|RESETERR
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sta SERCTL ; Allow TX-IRQ to hang RX-IRQ (no receive while transmitting)
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2013-05-09 11:56:54 +00:00
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sta TxDone
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2024-02-09 00:09:16 +00:00
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plp ; Restore processor and interrupt enable
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2009-09-20 14:22:04 +00:00
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@L1:
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_OK
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.assert SER_ERR_OK = 0, error
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2013-05-09 11:56:54 +00:00
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tax
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rts
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_STATUS: Return the status in the variable pointed to by ptr1.
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2009-09-20 14:22:04 +00:00
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; Must return an SER_ERR_xx code in a/x.
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2018-11-26 20:28:40 +00:00
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SER_STATUS:
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2024-02-09 00:09:16 +00:00
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lda SerialStat
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2024-02-11 23:12:27 +00:00
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sta (ptr1)
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2013-05-09 11:56:54 +00:00
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ldx #$00
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txa ; Return code = 0
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rts
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_IOCTL: Driver defined entry point. The wrapper will pass a pointer to ioctl
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2009-09-20 14:22:04 +00:00
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; specific data in ptr1, and the ioctl code in A.
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; Must return an SER_ERR_xx code in a/x.
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2018-11-26 20:28:40 +00:00
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SER_IOCTL:
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2023-02-26 19:03:41 +00:00
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lda #SER_ERR_INV_IOCTL
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ldx #0 ; return value is char
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2013-05-09 11:56:54 +00:00
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rts
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2009-09-20 14:22:04 +00:00
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;----------------------------------------------------------------------------
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2018-11-26 20:28:40 +00:00
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; SER_IRQ: Called from the builtin runtime IRQ handler as a subroutine. All
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2009-09-20 14:22:04 +00:00
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; registers are already saved, no parameters are passed, but the carry flag
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; is clear on entry. The routine must return with carry set if the interrupt
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; was handled, otherwise with carry clear.
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;
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; Both the Tx and Rx interrupts are level sensitive instead of edge sensitive.
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; Due to this bug you have to disable the interrupt before clearing it.
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2018-11-26 20:28:40 +00:00
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SER_IRQ:
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2013-05-09 11:56:54 +00:00
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lda INTSET ; Poll all pending interrupts
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and #SERIAL_INTERRUPT
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bne @L0
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clc
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rts
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2009-09-20 14:22:04 +00:00
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@L0:
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2013-05-09 11:56:54 +00:00
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bit TxDone
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bmi @tx_irq ; Transmit in progress
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2024-02-09 00:09:16 +00:00
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ldx SERDAT ; Read received data
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lda contrl
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and #PAREN ; Parity enabled implies SER_PAR_EVEN or SER_PAR_ODD
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2024-02-09 12:54:00 +00:00
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tay
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2024-02-10 21:15:05 +00:00
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ora #OVERRUN|FRAMERR|RXBRK
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2024-02-11 23:12:27 +00:00
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and SERCTL ; Check presence of relevant error flags in SERCTL
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2024-02-09 00:09:16 +00:00
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beq @rx_irq ; No errors so far
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2013-05-09 11:56:54 +00:00
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tsb SerialStat ; Save error condition
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2024-02-09 00:09:16 +00:00
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bit #RXBRK ; Check for break signal
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2013-05-09 11:56:54 +00:00
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beq @noBreak
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2024-02-09 00:09:16 +00:00
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2013-05-09 11:56:54 +00:00
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stz TxPtrIn ; Break received - drop buffers
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stz TxPtrOut
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stz RxPtrIn
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stz RxPtrOut
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2009-09-20 14:22:04 +00:00
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@noBreak:
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2024-02-09 10:42:52 +00:00
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bra @exit0
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2024-02-09 00:09:16 +00:00
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2009-09-20 14:22:04 +00:00
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@rx_irq:
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2024-02-09 12:54:00 +00:00
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tya
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bne @2 ; Parity was enabled so no marker bit check needed
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lda contrl
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eor SERCTL ; Should match current parity bit
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and #PARBIT ; Check for mark or space value
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bne @exit0
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@2:
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2009-09-20 14:22:04 +00:00
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txa
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2013-05-09 11:56:54 +00:00
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ldx RxPtrIn
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sta RxBuffer,x
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2009-09-20 14:22:04 +00:00
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txa
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inx
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2013-05-09 11:56:54 +00:00
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cpx RxPtrOut
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beq @1
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stx RxPtrIn
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bra @IRQexit
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2009-09-20 14:22:04 +00:00
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@1:
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2013-05-09 11:56:54 +00:00
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sta RxPtrIn
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lda #$80
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tsb SerialStat
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2024-02-09 10:42:52 +00:00
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bra @exit0
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2024-02-09 00:09:16 +00:00
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2009-09-20 14:22:04 +00:00
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@tx_irq:
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2024-02-09 00:09:16 +00:00
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ldx TxPtrOut ; Have all bytes been sent?
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2013-05-09 11:56:54 +00:00
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cpx TxPtrIn
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beq @allSent
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2009-09-20 14:22:04 +00:00
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2013-05-09 11:56:54 +00:00
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lda TxBuffer,x ; Send next byte
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sta SERDAT
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inc TxPtrOut
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2009-09-20 14:22:04 +00:00
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@exit1:
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2013-05-09 11:56:54 +00:00
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lda contrl
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2024-02-09 00:09:16 +00:00
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ora #TXINTEN|RESETERR
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2013-05-09 11:56:54 +00:00
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sta SERCTL
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bra @IRQexit
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2009-09-20 14:22:04 +00:00
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@allSent:
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2013-05-09 11:56:54 +00:00
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lda SERCTL ; All bytes sent
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2024-02-09 00:09:16 +00:00
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bit #TXEMPTY
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2013-05-09 11:56:54 +00:00
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beq @exit1
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bvs @exit1
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stz TxDone
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2024-02-09 10:42:52 +00:00
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@exit0:
|
2013-05-09 11:56:54 +00:00
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lda contrl
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2024-02-09 00:09:16 +00:00
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ora #RXINTEN|RESETERR ; Re-enable receive interrupt
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2013-05-09 11:56:54 +00:00
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sta SERCTL
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2024-02-09 00:09:16 +00:00
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@IRQexit:
|
2013-05-09 11:56:54 +00:00
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lda #SERIAL_INTERRUPT
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sta INTRST
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clc
|
2009-09-20 14:22:04 +00:00
|
|
|
rts
|