2000-05-28 13:40:48 +00:00
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;
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; C64 generic definitions. Stolen from Elite128
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;
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; ---------------------------------------------------------------------------
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; Zero page, Commodore stuff
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2015-09-28 15:27:39 +00:00
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VARTAB := $2D ; Pointer to start of BASIC variables
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MEMSIZE := $37 ; Pointer to highest BASIC RAM location (+1)
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2013-08-25 04:43:23 +00:00
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TXTPTR := $7A ; Pointer into BASIC source code
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2020-11-28 11:03:48 +00:00
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STATUS := $90 ; Kernal I/O completion status
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2003-10-17 00:53:14 +00:00
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TIME := $A0 ; 60 HZ clock
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2013-05-09 11:56:54 +00:00
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FNAM_LEN := $B7 ; Length of filename
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SECADR := $B9 ; Secondary address
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DEVNUM := $BA ; Device number
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2003-10-17 00:53:14 +00:00
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FNAM := $BB ; Pointer to filename
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2013-05-09 11:56:54 +00:00
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KEY_COUNT := $C6 ; Number of keys in input buffer
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2003-10-17 00:53:14 +00:00
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RVS := $C7 ; Reverse flag
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2013-05-09 11:56:54 +00:00
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CURS_FLAG := $CC ; 1 = cursor off
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CURS_BLINK := $CD ; Blink counter
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CURS_CHAR := $CE ; Character under the cursor
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CURS_STATE := $CF ; Cursor blink state
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SCREEN_PTR := $D1 ; Pointer to current char in text screen
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CURS_X := $D3 ; Cursor column
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CURS_Y := $D6 ; Cursor row
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CRAM_PTR := $F3 ; Pointer to current char in color RAM
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2015-10-05 09:47:43 +00:00
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FREKZP := $FB ; Five unused bytes
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2013-05-09 11:56:54 +00:00
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BASIC_BUF := $200 ; Location of command-line
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BASIC_BUF_LEN = 89 ; Maximum length of command-line
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2003-05-25 11:46:21 +00:00
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2003-10-17 00:53:14 +00:00
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CHARCOLOR := $286
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2013-05-09 11:56:54 +00:00
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CURS_COLOR := $287 ; Color under the cursor
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PALFLAG := $2A6 ; $01 = PAL, $00 = NTSC
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2000-05-28 13:40:48 +00:00
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2017-06-17 00:37:34 +00:00
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KBDREPEAT := $28a
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KBDREPEATRATE := $28b
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KBDREPEATDELAY := $28c
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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; Vector and other locations
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2013-05-09 11:56:54 +00:00
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IRQVec := $0314
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BRKVec := $0316
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NMIVec := $0318
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2000-05-28 13:40:48 +00:00
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2003-04-09 19:34:57 +00:00
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; ---------------------------------------------------------------------------
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; Screen size
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XSIZE = 40
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YSIZE = 25
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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; I/O: VIC
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2013-05-09 11:56:54 +00:00
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VIC := $D000
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VIC_SPR0_X := $D000
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VIC_SPR0_Y := $D001
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VIC_SPR1_X := $D002
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VIC_SPR1_Y := $D003
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VIC_SPR2_X := $D004
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VIC_SPR2_Y := $D005
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VIC_SPR3_X := $D006
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VIC_SPR3_Y := $D007
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VIC_SPR4_X := $D008
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VIC_SPR4_Y := $D009
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VIC_SPR5_X := $D00A
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VIC_SPR5_Y := $D00B
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VIC_SPR6_X := $D00C
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VIC_SPR6_Y := $D00D
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VIC_SPR7_X := $D00E
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VIC_SPR7_Y := $D00F
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VIC_SPR_HI_X := $D010
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VIC_SPR_ENA := $D015
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VIC_SPR_EXP_Y := $D017
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VIC_SPR_EXP_X := $D01D
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VIC_SPR_MCOLOR := $D01C
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2003-10-17 00:53:14 +00:00
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VIC_SPR_BG_PRIO := $D01B
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VIC_SPR_MCOLOR0 := $D025
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VIC_SPR_MCOLOR1 := $D026
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2013-05-09 11:56:54 +00:00
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VIC_SPR0_COLOR := $D027
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VIC_SPR1_COLOR := $D028
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VIC_SPR2_COLOR := $D029
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VIC_SPR3_COLOR := $D02A
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VIC_SPR4_COLOR := $D02B
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VIC_SPR5_COLOR := $D02C
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VIC_SPR6_COLOR := $D02D
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VIC_SPR7_COLOR := $D02E
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2003-10-17 00:53:14 +00:00
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2013-05-09 11:56:54 +00:00
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VIC_CTRL1 := $D011
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VIC_CTRL2 := $D016
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2003-10-17 00:53:14 +00:00
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2013-05-09 11:56:54 +00:00
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VIC_HLINE := $D012
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2003-10-17 00:53:14 +00:00
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2013-05-29 23:48:45 +00:00
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VIC_LPEN_X := $D013
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VIC_LPEN_Y := $D014
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2013-05-09 11:56:54 +00:00
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VIC_VIDEO_ADR := $D018
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2003-10-17 00:53:14 +00:00
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2013-05-09 11:56:54 +00:00
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VIC_IRR := $D019 ; Interrupt request register
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VIC_IMR := $D01A ; Interrupt mask register
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2003-10-17 00:53:14 +00:00
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VIC_BORDERCOLOR := $D020
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2013-05-09 11:56:54 +00:00
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VIC_BG_COLOR0 := $D021
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VIC_BG_COLOR1 := $D022
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VIC_BG_COLOR2 := $D023
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VIC_BG_COLOR3 := $D024
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2000-05-28 13:40:48 +00:00
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; 128 stuff:
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2013-05-09 11:56:54 +00:00
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VIC_KBD_128 := $D02F ; Extended kbd bits (visible in 64 mode)
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VIC_CLK_128 := $D030 ; Clock rate register (visible in 64 mode)
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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; I/O: SID
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2013-05-09 11:56:54 +00:00
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SID := $D400
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SID_S1Lo := $D400
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SID_S1Hi := $D401
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SID_PB1Lo := $D402
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SID_PB1Hi := $D403
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SID_Ctl1 := $D404
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SID_AD1 := $D405
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SID_SUR1 := $D406
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SID_S2Lo := $D407
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SID_S2Hi := $D408
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SID_PB2Lo := $D409
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SID_PB2Hi := $D40A
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SID_Ctl2 := $D40B
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SID_AD2 := $D40C
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SID_SUR2 := $D40D
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SID_S3Lo := $D40E
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SID_S3Hi := $D40F
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SID_PB3Lo := $D410
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SID_PB3Hi := $D411
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SID_Ctl3 := $D412
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SID_AD3 := $D413
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SID_SUR3 := $D414
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SID_FltLo := $D415
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SID_FltHi := $D416
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SID_FltCtl := $D417
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SID_Amp := $D418
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SID_ADConv1 := $D419
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SID_ADConv2 := $D41A
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SID_Noise := $D41B
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SID_Read3 := $D41C
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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; I/O: VDC (128 only)
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2013-05-09 11:56:54 +00:00
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VDC_INDEX := $D600
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VDC_DATA := $D601
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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2017-11-25 18:25:01 +00:00
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; I/O: Complex Interface Adapters
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2000-05-28 13:40:48 +00:00
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2013-05-09 11:56:54 +00:00
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CIA1 := $DC00
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2017-11-25 18:25:01 +00:00
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CIA1_PRA := $DC00 ; Port A
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CIA1_PRB := $DC01 ; Port B
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CIA1_DDRA := $DC02 ; Data direction register for port A
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CIA1_DDRB := $DC03 ; Data direction register for port B
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CIA1_TA := $DC04 ; 16-bit timer A
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CIA1_TB := $DC06 ; 16-bit timer B
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CIA1_TOD10 := $DC08 ; Time-of-day tenths of a second
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CIA1_TODSEC := $DC09 ; Time-of-day seconds
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CIA1_TODMIN := $DC0A ; Time-of-day minutes
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CIA1_TODHR := $DC0B ; Time-of-day hours
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CIA1_SDR := $DC0C ; Serial data register
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CIA1_ICR := $DC0D ; Interrupt control register
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CIA1_CRA := $DC0E ; Control register for timer A
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CIA1_CRB := $DC0F ; Control register for timer B
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2013-05-09 11:56:54 +00:00
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CIA2 := $DD00
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CIA2_PRA := $DD00
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CIA2_PRB := $DD01
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CIA2_DDRA := $DD02
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CIA2_DDRB := $DD03
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2017-11-25 18:25:01 +00:00
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CIA2_TA := $DD04
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CIA2_TB := $DD06
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2009-07-27 18:44:37 +00:00
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CIA2_TOD10 := $DD08
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CIA2_TODSEC := $DD09
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CIA2_TODMIN := $DD0A
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CIA2_TODHR := $DD0B
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2017-11-25 18:25:01 +00:00
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CIA2_SDR := $DD0C
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2013-05-09 11:56:54 +00:00
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CIA2_ICR := $DD0D
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CIA2_CRA := $DD0E
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CIA2_CRB := $DD0F
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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; Super CPU
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2013-05-09 11:56:54 +00:00
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SCPU_VIC_Bank1 := $D075
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SCPU_Slow := $D07A
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SCPU_Fast := $D07B
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2003-10-17 00:53:14 +00:00
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SCPU_EnableRegs := $D07E
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SCPU_DisableRegs:= $D07F
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2013-05-09 11:56:54 +00:00
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SCPU_Detect := $D0BC
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2000-05-28 13:40:48 +00:00
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; ---------------------------------------------------------------------------
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; Processor Port at $01
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2013-05-09 11:56:54 +00:00
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LORAM = $01 ; Enable the basic rom
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HIRAM = $02 ; Enable the kernal rom
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IOEN = $04 ; Enable I/O
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CASSDATA = $08 ; Cassette data
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CASSPLAY = $10 ; Cassette: Play
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CASSMOT = $20 ; Cassette motor on
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TP_FAST = $80 ; Switch Rossmoeller TurboProcess to fast mode
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2000-05-28 13:40:48 +00:00
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2013-05-09 11:56:54 +00:00
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RAMONLY = $F8 ; (~(LORAM | HIRAM | IOEN)) & $FF
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