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Added 6502 illegal instructions
git-svn-id: svn://svn.cc65.org/cc65/trunk@3022 b7a2c559-68d2-44c3-8de9-860c34a00d81
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cuz
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@ -309,6 +309,8 @@ The assembler accepts
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<itemize>
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<item>all valid 6502 mnemonics when in 6502 mode (the default or after the
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<tt><ref id=".P02" name=".P02"></tt> command was given).
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<item>all valid 6502 mnemonics plus a set of illegal instructions when in
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<ref id="6502X-mode" name="6502X mode">.
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<item>all valid 65SC02 mnemonics when in 65SC02 mode (after the
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<tt><ref id=".PSC02" name=".PSC02"></tt> command was given).
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<item>all valid 65C02 mnemonics when in 65C02 mode (after the
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@ -338,17 +340,36 @@ mnemonics:
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TSA is an alias for TSC
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</verb></tscreen>
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Evaluation of banked expressions in 65816 mode differs slightly from the
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official syntax:
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Instead of accepting a 24 bit address (something that is difficult for
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the assembler to determine and would have required one more special
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.import command), the bank and the absolute address in that bank are
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separated by a dot:
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<tscreen><verb>
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jsl 3.$1234 ; Call subroutine at $1234 in bank 3
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</verb></tscreen>
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<sect1>6502X mode<label id="6502X-mode"><p>
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6502X mode is an extension to the normal 6502 mode. In this mode, several
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mnemomics for illegal instructions of the NMOS 6502 CPUs are accepted. Since
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these instructions are illegal, there are no official mnemonics for them. The
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unofficial ones are taken from <htmlurl
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url="http://oxyron.net/graham/opcodes02.html"
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name="http://oxyron.net/graham/opcodes02.html">. Please note that only the
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ones marked as "stable" are supported. The following table uses information
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from the mentioned web page, for more information, see there.
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<itemize>
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<item><tt>ALR: A:=(A and #{imm})*2;</tt>
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<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode $0B.
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<item><tt>ARR: A:=(A and #{imm})/2;</tt>
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<item><tt>AXS: X:=A and X-#{imm};</tt>
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<item><tt>DCP: {adr}:={adr}-1; A-{adr};</tt>
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<item><tt>ISC: {adr}:={adr}+1; A:=A-{adr};</tt>
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<item><tt>LAS: A,X,S:={adr} and S;</tt>
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<item><tt>LAX: A,X:={adr};</tt>
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<item><tt>RLA: {adr}:={adr}rol; A:=A and {adr};</tt>
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<item><tt>RRA: {adr}:={adr}ror; A:=A adc {adr};</tt>
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<item><tt>SAX: {adr}:=A and X;</tt>
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<item><tt>SLO: {adr}:={adr}*2; A:=A or {adr};</tt>
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<item><tt>SRE: {adr}:={adr}/2; A:=A xor {adr};</tt>
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</itemize>
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<sect1>Number format<p>
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@ -2955,9 +2976,10 @@ Here's a list of all control commands and a description, what they do:
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Switch the CPU instruction set. The command is followed by a string that
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specifies the CPU. Possible values are those that can also be supplied to
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the <tt><ref id="option--cpu" name="--cpu"></tt> command line option,
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namely: 6502, 65SC02, 65C02, 65816 and sunplus. Please note that support
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for the sunplus CPU is not available in the freeware version, because the
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instruction set of the sunplus CPU is "proprietary and confidential".
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namely: 6502, 6502X, 65SC02, 65C02, 65816 and sunplus. Please note that
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support for the sunplus CPU is not available in the freeware version,
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because the instruction set of the sunplus CPU is "proprietary and
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confidential".
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See: <tt><ref id=".CPU" name=".CPU"></tt>,
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<tt><ref id=".IFP02" name=".IFP02"></tt>,
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@ -147,7 +147,7 @@ static const struct {
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};
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/* Instruction table for the 6502 with illegal instructions */
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#define INS_COUNT_6502X 57
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#define INS_COUNT_6502X 70
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static const struct {
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unsigned Count;
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InsDesc Ins[INS_COUNT_6502X];
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@ -155,8 +155,12 @@ static const struct {
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INS_COUNT_6502X,
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{
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{ "ADC", 0x080A26C, 0x60, 0, PutAll },
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{ "ALR", 0x0800000, 0x4B, 0, PutAll }, /* X */
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{ "ANC", 0x0800000, 0x0B, 0, PutAll }, /* X */
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{ "AND", 0x080A26C, 0x20, 0, PutAll },
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{ "ARR", 0x0800000, 0x6B, 0, PutAll }, /* X */
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{ "ASL", 0x000006e, 0x02, 1, PutAll },
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{ "AXS", 0x0800000, 0xCB, 0, PutAll }, /* X */
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{ "BCC", 0x0020000, 0x90, 0, PutPCRel8 },
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{ "BCS", 0x0020000, 0xb0, 0, PutPCRel8 },
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{ "BEQ", 0x0020000, 0xf0, 0, PutPCRel8 },
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@ -174,6 +178,7 @@ static const struct {
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{ "CMP", 0x080A26C, 0xc0, 0, PutAll },
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{ "CPX", 0x080000C, 0xe0, 1, PutAll },
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{ "CPY", 0x080000C, 0xc0, 1, PutAll },
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{ "DCP", 0x000A26C, 0xC3, 0, PutAll }, /* X */
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{ "DEC", 0x000006C, 0x00, 3, PutAll },
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{ "DEX", 0x0000001, 0xca, 0, PutAll },
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{ "DEY", 0x0000001, 0x88, 0, PutAll },
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@ -181,9 +186,12 @@ static const struct {
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{ "INC", 0x000006c, 0x00, 4, PutAll },
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{ "INX", 0x0000001, 0xe8, 0, PutAll },
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{ "INY", 0x0000001, 0xc8, 0, PutAll },
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{ "ISC", 0x000A26C, 0xE3, 0, PutAll }, /* X */
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{ "JAM", 0x0000001, 0x02, 0, PutAll }, /* X */
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{ "JMP", 0x0000808, 0x4c, 6, PutJMP },
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{ "JSR", 0x0000008, 0x20, 7, PutAll },
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{ "LAS", 0x0000200, 0xBB, 0, PutAll }, /* X */
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{ "LAX", 0x000A30C, 0xA3, 1, PutAll }, /* X */
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{ "LDA", 0x080A26C, 0xa0, 0, PutAll },
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{ "LDX", 0x080030C, 0xa2, 1, PutAll },
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{ "LDY", 0x080006C, 0xa0, 1, PutAll },
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@ -194,14 +202,19 @@ static const struct {
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{ "PHP", 0x0000001, 0x08, 0, PutAll },
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{ "PLA", 0x0000001, 0x68, 0, PutAll },
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{ "PLP", 0x0000001, 0x28, 0, PutAll },
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{ "RLA", 0x000A26C, 0x23, 0, PutAll }, /* X */
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{ "ROL", 0x000006F, 0x22, 1, PutAll },
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{ "ROR", 0x000006F, 0x62, 1, PutAll },
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{ "RRA", 0x000A26C, 0x63, 0, PutAll }, /* X */
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{ "RTI", 0x0000001, 0x40, 0, PutAll },
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{ "RTS", 0x0000001, 0x60, 0, PutAll },
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{ "SAX", 0x000810C, 0x83, 1, PutAll }, /* X */
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{ "SBC", 0x080A26C, 0xe0, 0, PutAll },
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{ "SEC", 0x0000001, 0x38, 0, PutAll },
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{ "SED", 0x0000001, 0xf8, 0, PutAll },
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{ "SEI", 0x0000001, 0x78, 0, PutAll },
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{ "SLO", 0x000A26C, 0x03, 0, PutAll }, /* X */
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{ "SRE", 0x000A26C, 0x43, 0, PutAll }, /* X */
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{ "STA", 0x000A26C, 0x80, 0, PutAll },
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{ "STX", 0x000010c, 0x82, 1, PutAll },
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{ "STY", 0x000002c, 0x80, 1, PutAll },
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@ -406,7 +419,7 @@ static const struct {
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unsigned Count;
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InsDesc Ins[INS_COUNT_65816];
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} InsTab65816 = {
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INS_COUNT_65816,
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INS_COUNT_65816,
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{
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{ "ADC", 0x0b8f6fc, 0x60, 0, PutAll },
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{ "AND", 0x0b8f6fc, 0x20, 0, PutAll },
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@ -544,7 +557,7 @@ unsigned char EATab [9][AMI_COUNT] = {
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},
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{ /* Table 1 */
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0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
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0x14, 0x1C, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,
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0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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},
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@ -552,7 +565,7 @@ unsigned char EATab [9][AMI_COUNT] = {
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0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
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0x00
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0x00
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},
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{ /* Table 3 */
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0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
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