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Fixed inline assembler problems with instructions where implicit means

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actually accumulator addressing. These went through and caused the
optimizer to behave strangely.


git-svn-id: svn://svn.cc65.org/cc65/trunk@3164 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
cuz
2004-07-18 09:34:52 +00:00
parent 9b2834ef7e
commit 1fb5967496
3 changed files with 31 additions and 26 deletions
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6
src/cc65/codeseg.c
View File

@@ -289,8 +289,12 @@ static CodeEntry* ParseInsn (CodeSeg* S, LineInfo* LI, const char* L)
switch (*L) {
case '\0':
/* Implicit */
/* Implicit or accu */
if (OPC->Info & OF_NOIMP) {
AM = AM65_ACC;
} else {
AM = AM65_IMP;
}
break;
case '#':

12
src/cc65/opcodes.c
View File

@@ -77,7 +77,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
OF_SETF /* flags */
OF_SETF | OF_NOIMP /* flags */
},
{ OP65_BCC, /* opcode */
"bcc", /* mnemonic */
@@ -217,7 +217,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
OF_SETF /* flags */
OF_SETF | OF_NOIMP /* flags */
},
{ OP65_DEX, /* opcode */
"dex", /* mnemonic */
@@ -252,7 +252,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
OF_SETF /* flags */
OF_SETF | OF_NOIMP /* flags */
},
{ OP65_INX, /* opcode */
"inx", /* mnemonic */
@@ -364,7 +364,7 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
OF_SETF /* flags */
OF_SETF | OF_NOIMP /* flags */
},
{ OP65_NOP, /* opcode */
"nop", /* mnemonic */
@@ -441,14 +441,14 @@ const OPCDesc OPCTable[OP65_COUNT] = {
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
OF_SETF /* flags */
OF_SETF | OF_NOIMP /* flags */
},
{ OP65_ROR, /* opcode */
"ror", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
OF_SETF /* flags */
OF_SETF | OF_NOIMP /* flags */
},
/* Mark RTI as "uses all registers but doesn't change them", so the
* optimizer won't remove preceeding loads.

1
src/cc65/opcodes.h
View File

@@ -174,6 +174,7 @@ typedef enum {
#define OF_REG_INCDEC 0x0400U /* A register increment or decrement */
#define OF_SETF 0x0800U /* Insn will set all load flags (not carry) */
#define OF_CMP 0x1000U /* A compare A/X/Y instruction */
#define OF_NOIMP 0x2000U /* Implicit addressing mode is actually A */
/* Combined infos */
#define OF_BRA (OF_UBRA | OF_CBRA) /* Operation is a jump/branch */