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If the previous insn may be skipped, we cannot simply predict the output values of the registers.

This commit is contained in:
acqn 2020-01-03 08:20:28 +08:00 committed by Oliver Schmidt
parent 53eb6a948d
commit 2220c58f51

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@ -1560,9 +1560,9 @@ void CS_GenRegInfo (CodeSeg* S)
/* If this insn is a branch on zero flag, we may have more info on
** register contents for one of both flow directions, but only if
** there is a previous instruction.
** we've gone through a previous instruction.
*/
if ((E->Info & OF_ZBRA) != 0 && (P = CS_GetPrevEntry (S, I)) != 0) {
if (LabelCount == 0 && (E->Info & OF_ZBRA) != 0 && (P = CS_GetPrevEntry (S, I)) != 0) {
/* Get the branch condition */
bc_t BC = GetBranchCond (E->OPC);